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Faraday, NemoChips develop low power mobile platform

Posted: 30 May 2008 ?? ?Print Version ?Bookmark and Share

Keywords:mobile platform? Common Power Format. Application processor?

Faraday Technology Corp. and NemoChip have partnered to develop next-generation low power mobile platform based on Cadence Low-Power Solution.

NemoChips has taped out a low-power mobile video platform SoC leveraging Faraday's SoCompiler design services employing the Common Power Format (CPF)-enabled Cadence Low-Power Solution. The design took two months from netlist to tape-out while achieving a >99 percent leakage reduction and 65 percent dynamic power reduction using advanced techniques such as dynamic voltage and frequency scaling, multi-supply voltages, and power-shut off. ASIC customers designing complex and power sensitive SoCs can benefit from this methodology to reduce time to market as well as to reduce implementation risk.

The NemoChips low power, high performance, multimedia application processor is targeted for use within mobile terminals, including mobile handsets, portable media players, portable navigation devices and car entertainment systems. It delivers DVD quality video to mobile devices without video format limitation.

"We are pleased with the performance, power savings and rapid tape-out of our mobile application processor chip, which provides desktop-like multimedia experience to our customer on handheld devices without sacrificing battery life," said Lifeng Zhao, president of NemoChips. "Faraday has clearly demonstrated strong expertise in implementing complex low-power chips."

Faraday's SoCompiler Design Services team used the Si2 standard CPF to specify power-saving techniques early, so the information could be reused throughout the design process. The Cadence Low-Power Solution integrates logic design, verification, and implementation with CPF, automating power-saving design techniques like dynamic voltage and frequency scaling without impacting delivery schedules.

In the early stages of the design, Faraday used Cadence Conformal LP, Logic Equivalence Checker, and Faraday's internal design kit, to handle best-in-class verification for this complex low power design. The verification includes more than 30 automatic checking procedures in the design flow, and it can be automatically performed in a few minutes. Cadence Conformal Low Power technologies are highly complementary and help Faraday to extend its ability to provide low power technology to design bigger, faster chips.

"By working with Power Forward Initiative members Cadence and UMC, we are able to help Nemochips meet a set of stringent power requirements using a solution that provided a 2x productivity improvement, enabling delivery within a very short design cycle," said George Hwang, VP of international business of Faraday.

"Faraday's fast, low-risk delivery of a low-power mobile platform to NemoChips demonstrates the value of a highly automated and holistic low-power solution," said Chi-Ping Hsu, corporate VP, IC digital and power forward at Cadence. "We're excited about the continuing silicon successes of CPF-based Cadence Low Power Solution. And we're grateful for Faraday's recent contribution to "A Practical Guide to Low-Power DesignUser experience with CPF," which is an online guide to low power design based entirely on actual user experience."

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