Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Embedded

Understand, test OCP SystemC channel models

Posted: 02 Jun 2008 ?? ?Print Version ?Bookmark and Share

Keywords:Electronic System Level design methodology? SoC design. OCP SystemC?

As VLSI process technology continuously advances, the SoC design methodology has become a main design trend for semiconductor products. A single SoC containing multi-million gates for audio/video/communication applications is now commonplace in the electronics industry.

However, challenges arise due to the high complexity of SoC design. For example, the simulation time to verify an SoC is often too long to meet the time-to-market requirement. In general the simulation speed relates to the abstraction level of the SoC description. Although Verilog and VHDL, the two main hardware description languages employed today, support abstraction levels up to the functional level, the nature of Verilog and VHDL restricts them from achieving high simulation speed. Also the lack of high-level programming language features such as inheritance, reference, thread, and dynamic resolution makes it hard to use Verilog and VHDL to develop high-level models and systems.

View the PDF document for more information.

Article Comments - Understand, test OCP SystemC channel...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top