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TSMC stirs IC designs using 40nm node

Posted: 05 Jun 2008 ?? ?Print Version ?Bookmark and Share

Keywords:DFM? EDA? chip design?

Making way for next-generation chips, Taiwan Semiconductor Manufacturing Co. Ltd will roll out its latest design methodology for IC production at the 40nm node.

TSMC's Reference Flow 9.0 is a collection of EDA, design-for-manufacturing (DFM) and other design tools used to enable chip designs for its new 40nm foundry process. The flow includes support for a second EDA power standard; enhanced statistical timing analysis; and new hierarchical DFM capabilities.

At that node, it also narrows the roster of the company's list of tool vendors to Cadence Design Systems, Synopsys, Magma, Mentor, Apache, Extreme-DA, CLK DA and Azuro.

In Reference Flow 9.0, TSMC now supports the industry-standard unified power format (UPF) language, which is backed by Synopsys, Mentor Graphics Inc., and Magma. UPF supports integrated low-power design flows from RTL to silicon.

Previously, TSMC unveiled its design methodology for IC production at the challenging 45nm node, dubbed Reference Flow 8.0. The suite provided a ringing endorsement to Cadence's rival low-power EDA standard, dubbed the common power format (CPF). Reference Flow 9.0 supports both CPF and UPF.

TSMC has moved into production at both the 40nm and 45nm nodes. In March, TSMC unveiled its 40nm process. The process is an interim, "half node" step toward the 32nm process node, which TSMC expects to ramp starting late next year.

Over the years, TSMC has rolled out reference flows at the various process nodes to help customers reduce their product development times. As part of those efforts, the company has also offered limited design services and developed its own physical-layer intellectual property (IP).

In April, the world's largest silicon foundry showed a new and possibly controversial strategy that involved more collaboration in the early stages of the IC design process. The so-called open innovation platform (OIP) consists of a suite of design tools and IP to help customers with their DFM efforts.

But it could also possibly cause a major stir in the industry, as the silicon foundry giant wants more of the IC pie and appears to be encroaching on the turf of the third-party EDA, IP, packaging and test communities.

Officials from TSMC argued that OIP is not a competitive offering. "OIP helps customers design and innovate faster," said Tom Quan, deputy director of design services marketing, TSMC.

"OIP enables TSMC and customers to collaborate better in terms of having the right pieces?such as EDA tools, IP and process platforms?in place," he added.

"Like before, TSMC only provides limited IC design service capabilities. The company gives 'very backend stuff' in terms of IC design, but we are not doing designs for customers," he noted.

He stressed that the real goal for TSMC is to collaborate much deeper with our ecosystem partners.

To provide more collaboration, TSMC rolled out Reference Flow 9.0. The flow provides a reference of qualified design tools and flows that give designers a proved path from specification to tape-out.

There are similarities between Reference Flow 8.0 and 9.0. Reference Flow 9.0 also includes a number of power reduction techniques, including TSMC's clock gating design flow for dynamic power reduction. The new low-power clock tree synthesis supports multimode/multicorner, and on-chip variation to reduce active and leakage power.

The flow now supports stage-based on-chip variation, as well as design-specific on-chip variation derived from statistical analysis. In addition, new transistor-level path-based statistical static timing analysis is launched to enhance timing accuracy and reduce the need for precharacterized cell libraries.

Reference Flow 9.0 provides improvements in DFM. It is believed to speed up DFM analysis for large designs and address potential parametric performance shifts caused by DFM effects.

It also supports the following third-party EDA vendors and tool:

  • Cadence: Full tool suite, RTL Compiler, SoC Encounter, QRC extraction, ETS, VoltageStorm, Encounter test, and DFM tools.

  • Synopsys: Full tool suite, Design/Power/IC compilers, DFT, PrimeTime, PrimeRail, Star-RCXT, Hercules, and PrimeYield DFM tools.

  • Magma: Full tool suite, Talus system, Quartz SSTA, Quartz DFM, Quartz DRC/LVS.

  • Mentor: Full physical verification and DFM tool suite, Calibre, Calibre xRC, Calibre nmLVS, Calibre LFD, Calibre CMP Analyzer, Calibre YieldAnalyzer, and DFT & ATPG tools.

  • Apache: RedHawk, RedHawk-ALP, Sentinel-SSO.

  • Extreme-DA: GoldTime STA and SSTA


  • Azuro: Power Centric CTS

- Mark LaPedus
EE Times

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