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eInfochips launches IP tool for improved functionality

Posted: 10 Jun 2008 ?? ?Print Version ?Bookmark and Share

Keywords:verification? IP? SystemVerilog? code?

eInfochips Ltd launched what it claims as the first SystemVerilog verification IP that complies with the Open Verification Methodology and Advanced Verification Methodology (AVM) 3.0.

The AVM 3.0 was developed with Mentor Graphics Corp.

The company said its new tools would enable designers to better use key SystemVerilog functionality while cutting verification cycle times for designs that use standard interfaces such as the advanced microcontroller bus architecture protocol. "The verification IP includes building blocks needed for DUT for system-level verification," it added.

"Compliance with AVM 3.0 integrates verification techniques like constrained-random stimulus, functional coverage and assertions into a single transaction-level modeling framework implemented in both SystemC and SystemVerilog," it noted.

The IP includes verification component code, release notes and a test suite. The verification component is also available from eInfochips.

- K.C. Krishnadas
EE Times

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