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Xilinx tips coding solution for LTE wireless systems

Posted: 10 Jun 2008 ?? ?Print Version ?Bookmark and Share

Keywords:programmable turbo coding? LTE? W-CDMA? HSDPA?

Xilinx Inc. has made available a performance-optimized programmable turbo coding solutions for LTE wireless systems. The new Xilinx 3GPP LTE Turbo Encoder and Decoder LogiCORE offerings deliver throughput speeds of up to 200Mbit/s with the embedded DSP capabilities of Spartan and Virtex FPGAs to meet the voice and ever-increasing data communications requirements imposed on modern wireless systems by the evolving LTE standard.

Turbo Codes were first deployed commercially in 3G wireless systems, primarily W-CDMA/HSDPA base station applications. These function as an error correction method to ensure the optimum transfer of communications with performance levels approaching the theoretical Shannon limit (max information transfer rate over a noisy channel). The combination of the new Xilinx turbo coding and XtremeDSP solutions address the even greater throughput demands of 3GPP LTE systems currently in development, in order to meet the aggressive system latency reductions proposed in the new LTE standard. The cores are also designed to adapt rapidly to new and evolving requirements, such as the evolution of TD-SCDMA into the proposed TDD variant of LTE.

"With the release of the 3GPP LTE Turbo Encoder and Decoder, product developers can leverage the vast signal processing capabilities within our FPGAs to free up their system design," said Mark Quartermain, senior manager of baseband processing for the Xilinx processing solutions group. "These provide a robust communications platform which can both scale to meet different base station topologies from femtocells to macrocells, and be very simply updated should the Turbo parameters change as the LTE standard goes through the final ratification process."

Optimized for performance
The throughput delivered by the Xilinx 3GPP LTE Turbo Decoder LogiCORE solution exceeds the performance of competitive offerings by a factor of five, said the company. This enables developers to offload the complex, high-performance decoder function from the rest of the baseband solution, which in turn allows them to use more cost-effective DSPs for the remaining less performance-critical baseband functions. Developers can also trade off design size against throughput performance by simply selecting the number of processing units available to the decoder function within the Xilinx FPGA, thus ensuring that only the smallest possible device is needed to meet system performance criteria.

The Xilinx 3GPP LTE Turbo Decoder offers features that include complete Interleaver function, full 3GPP LTE block size range (188 block sizes, ranging from 40-6,144), dynamically selectable number of iterations 1-15 and multiple (2, 4, 8) processing units with intelligent scheduler function. Other features are MAX, MAX_SCALE and MAX (Log-MAP) algorithms; bit accurate C model available for fast simulation of BER performance and support for Spartan-3, Spartan-3A DSP, Virtex-4 and Virtex-5 FPGAs.

The 3GPP LTE Turbo Encoder and Decoder LogiCORE solutions are now shipping with the latest release of the Xilinx CORE Generator software. They are priced at $1,500 for the Turbo Encoder and $15,000 for the Turbo Decoder.

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