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Implementing DDR2-400 memory interfaces in Spartan-3A FPGAs

Posted: 09 Jun 2008 ?? ?Print Version ?Bookmark and Share

Keywords:DDR2-400? memory interfaces? FPGAs?

High-performance consumer products and their requirement for low-cost, high-bandwidth memory create demand for high-performance DDR2 memory interfaces. Xilinx offers a Memory Interface Generator (MIG) integrated in the CORE Generator software for ultimate design flexibility and ease-of-use. MIG is a free, user-friendly tool designed to create memory interfaces in unencrypted RTL. This tool supports multiple memory architectures across a variety of FPGA selections, providing system designers with the flexibility to easily customize their own design.

Spartan-3A FPGAs with the higher speed grade (-5) have been specified for operation up to DDR2-333 using a 166MHz clock, while lower speed grade (-4) devices have been specified for operation up to DDR2-266 using a 133MHz clock. Based on demand for even higher performance, Xilinx has validated a DDR2-400 (200MHz clock) memory interface in Spartan-3A FPGAs with the higher speed grade (-5). The validation results also apply to Spartan-3AN and Spartan-3A DSP FPGAs with the higher speed grade (-5).

The DDR2-400 memory interface discussed in this application note is derived from the default output of MIG. The design is fully verified in hardware using Spartan-3A FPGAs with the higher speed grade (-5) assembled on Spartan-3A Starter Kits. The validation effort includes characterization at different process corners, as well as temperature and voltage variations that meet commercial grade requirements.

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