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ESL methods for optimizing a multimedia phone chip

Posted: 11 Jun 2008 ?? ?Print Version ?Bookmark and Share

Keywords:ESL methods? multimedia phone chip? SoC architecture?

By Danilo Piergentili, David Coupe
NXP Semiconductors

Our team is chartered to validate and optimize the architecture of our NXP mobile phone chips. This is a very challenging application domain, as an ever increasing set of multi-media and wireless communication functions need to be integrated into one SoC. Next to a growing number of communication standards, today's mobile phones support a large variety of multi-media applications like MP3 audio, video recording and playback, and digital still camera.

The trend towards high-quality multimedia content and higher communication bandwidth drastically increases the complexity of the underlying SoC architecture. In previous designs a single application processor was sufficient to run the rather simple phone software and to control the modem subsystem. Today numerous dedicated IP blocks are necessary to perform the multimedia functions with the required performance and energy efficiency.

Block diagram of a multimedia mobile phone
The high-level block-diagram of the multimedia subsystem of a mobile phone is depicted in Figure 1. The four components on the top are initiators on the bus, whereas the multi-port memory controller is a target.

The MCU runs the high-level application software, like e.g. user-interface, personal information management, etc., and controls the other components in the system.

The camera interface provides two main functions. It delivers YUV encoded data from a continuous incoming dataflow from the sensor (viewfinder function). It also delivers JPEG compressed frames either for single-shot or multi-shot mode (capture function). In any case, the produced data hits memory as frame buffers with variable size (QVGA for viewfinder, 3Mpixel or more for JPEG data).

The rendering engine reads the data produced by the camera interface blocks and combines it with the man machine graphic interface. The rendering process includes color conversion, affine transformations (translation, rotation, scaling, mirroring, shearing), and blending operations. In viewfinder mode the camera interface produces YUV data whereas the man machine interface graphic is typically in RGB format. The rendering engine will produce a combined RGB image in the main memory.

The display controller fetches the RGB frame from the memory and shifts the data to the frame buffer of the LCD screen. It acts like a smart DMA with basic color format conversion.

Interconnect and memory subsystems of the platform are essentially the backbone of the entire SoC, and have to deliver the required communication bandwidth for all the IP blocks. It combines access to internal memory resources as well as access to common external memory.

Design time performance analysis issues
The goal of the architecture definition phase is to determine the optimal configuration of the design parameters in interconnect and memory subsystems, in order to deliver sufficient performance at minimal cost. In the past, the performance requirements were analyzed using spread-sheets. However, this static performance analysis approach is not applicable for the complexity of today's SoC platforms.

Multiple Initiators: As shown in the block diagram, we have a much higher number of IP blocks, which act as masters on the interconnect architecture.

Dynamic traffic: The traffic generated by the multimedia accelerators is rather bursty and greatly varies depending on use cases. As an example, a viewfinder operation will deliver quite regular memory access since the data is processed in raster scan order. On the other hand, functions like video encoding or decoding tend to exhibit scattered memory accesses, especially with the latest generation of video codecs. Another example is the influence of the frame buffer organization on the memory accesses: a coplanar organization will provide quite linear accesses, whereas a planar organization will require interleaved accesses through several frame buffer planes. An other factor influencing the traffic pattern is the dimension of the accessed objects: single dimension objects will again provide linear accesses, whereas the stride of 2-D objects will induce scattered and interleaved accesses. The combination of all possible configurations rapidly exceeds the capabilities of performance analysis using spread-sheets.

Arbitration: To cope with such a complex workload, we need multiple levels of arbitration and queuing in the bus matrix and in the multi-port memory controller. This hierarchical arbitration mechanism cannot be accurately predicted without a proper system simulation environment.

QoS: The memory controller offers advanced QoS features like bandwidth reservation for the multimedia blocks and a low latency access for the MCU.

Figure 1: The high-level block-diagram of the multimedia subsystem of a mobile phone.

This results in the following set of configuration parameters, which should be optimized by the architect:

Interconnect: bus-width, clock-period, topology, arbitration algorithm, priorities.

Memory Controller: bus-width, number of ports, low latency versus high bandwidth port, buffering, number of access beats.


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