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TSMC targets to unify 32nm design flow

Posted: 12 Jun 2008 ?? ?Print Version ?Bookmark and Share

Keywords:design flow? TSMC 32nm DFM? EDA tool?

Facing the 32nm challenge, Taiwan Semiconductor Manufacturing Co. Ltd is putting the pedal to the metal with a new design-for-manufacturing scheme.

TSMC's Unified Design For Manufacturing (UDFM) architecture, is touted as giving chipmakers unprecedented access!at no charge!to its proprietary simulator, DFM models and other production information for 32nm.The goal is to give IC makers a head start with TSMC's 32nm process, which is expected to move into production by the end of 2009.

Other leading-edge foundries!including IBM Corp.'s "fab club" (Advanced Micro Devices, Chartered Semiconductor, Freescale Semiconductor, Infineon Technologies, Samsung Electronics, STMicroelectronics and Toshiba) and United Microelectronics Corp.!are taking similar steps on the design automation and DFM fronts in hopes of making the 32nm transition somewhat less painful and costly.

Prepping for 32nm era
The question is whether those EDA and DFM tools will be ready for prime time. "The problem is complexity," said Gary Smith, founder and chief analyst of Gary Smith EDA. Chip design at 32nm "is capable of producing a billion-gate design. Most of the tools we are using today break at 100 million gates."

"If [the foundries and their customers] don't have a good handle on DFM today and a solid migration path to next-generation nodes, they'll find themselves sliding behind and in serious trouble by 2010, when 32nm is supposed to be ramping into early production," said Robert Lineback, an analyst with IC Insights Inc.

To address those challenges, TSMC will offer a DFM Design Kit (DDK) encapsulating two technologies over a common application programming interface: the foundry provider's proprietary simulator and its DFM data. Customers doing 32nm designs can download the encrypted DDK from TSMC's portal at no charge.

TSMC's DFM data includes three basic components: a lithography pattern checker, chemical-mechanical-polishing analysis and critical-area analysis for random defects. Besides the DFM data, the DDK includes the scripts, recipes, models and simulation engines for the company's IC manufacturing process. It also encapsulates the effects from DFM optimization, such as hot spots, optical proximity correction (OPC) and timing.

UDFM is an "exact copy" of the foundry's factory chain and process models, enabling faster product-development cycle times and better yields, said Tom Quan, deputy director of design services marketing at TSMC.

It is also a slight departure from TSMC's prior strategy. Currently, the foundry provides the DFM data and models to customers but does not offer its proprietary simulator. In that scenario, customers interpret and "align" the DFM data with their own third-party simulation and EDA tools.

The concept works at process technologies down to the 40nm node, but 32nm could be a different story, Quan said. Without more DFM data in the design chain, given the complexities of 32nm design, chipmakers could face a "misalignment between simulated and actual manufacturing hot spots." Translation: longer, more-costly development cycles.

TSMC's "copy exact" DFM methodology compensates for increasing manufacturing variances in advanced process technologies and improves the design alignment between TSMC and its customers, Quan said.

Foundry challenge
A growing number of IDMs is shifting more of their IC production to foundries. The question is whether those outsourcing specialists can deliver what they promise. "We're reaching the point where the pure-play foundry model will be tested as a growing number of major IDMs!such as TI, ST and others!turn their process R&D over to third-party manufacturers," Lineback said.

In his view, "The technical challenges will keep many mainstream IC designers and their companies from rushing to 32nm foundry services. More companies will hang back in the safe waters of mature processes, for economic and technical reasons."

IC design costs today range between $20 million and $50 million. At the 32nm node, they could hit an estimated $75 million per product. And many new and complex EDA tools will be required. "As far as design is concerned at 32nm, statistical timing tools are a must" because "variability is a killer," said Smith.

At 32nm, leading-edge foundries are expected to process wafers using 193nm immersion scanners and complex double-patterning techniques. In double patterning, the wafer is exposed twice, creating cost and complexity for chipmakers that now process wafers in scanners using single-exposure techniques. Double patterning will also require more OPC and phase-shift masks, likewise complicating design.

High-k catch-up
Meanwhile, TSMC appears to be playing catch-up in the emerging arena of high-k materials and metal gates!the key building blocks for scaling and enabling the next-generation transistor. Rival IBM and the other foundry members of its fab alliance recently tipped plans to offer high-k and metal gates to customers at 32nm in the second half of 2009. The companies have already released a design kit.

For the time being, the IBM fab group could have an edge over TSMC. "Our alliance is ahead with high-k and metal gates," said Ana Molnar Hunter, vice president of technology for Samsung Semiconductor Inc.'s System LSI foundry business.

But having a high-k/metal-gate design kit is only a piece of the puzzle. Like TSMC, the IBM group provides a common EDA and DFM reference flow built around an assortment of third-party tools. Samsung also offers a separate design reference flow for its ASIC customers, Hunter said.

"Working with EDA and DFM providers has become even more critical," she said. "DFM has become a necessity."

Taiwan foundry provider UMC is developing its 32nm process but has yet to articulate its strategy.

- Mark LaPedus
EE Times

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