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Synfora extends synthesis technology to FPGAs

Posted: 16 Jun 2008 ?? ?Print Version ?Bookmark and Share

Keywords:SoC? FPGA? video codecs? algorithmic synthesis?

Synfora Inc., specializing algorithmic synthesis tools used to design SoCs and FPGAs, recently announced the availability of PICO Extreme FPGA, which extends their algorithmic synthesis technology to FPGA devices.

Building on the strength of PICO Extreme for SoC design, PICO Extreme FPGA enables the implementation of dramatically larger and more complex FPGA subsystems such as video codecs, wireless modems or imaging pipelines and ensures more efficient implementation of complex algorithms than any other synthesis capability.

Using a recursive system composition methodology, this allows familiar design styles, reduces runtimes, and achieves unprecedented quality of results that compete with hand design. Recursive system composition is enabled by Synfora's innovative tightly coupled accelerator blocks (TCABs) technology. TCABs allow users to designate parts of their algorithm as custom building blocks. These application-specific building blocks are C procedures that can be designed and verified standalone. The PICO compiler then automatically integrates and schedules these blocks as if they were primitive computing elements. This process can be repeated to an arbitrary depth so that a building block can contain multiple building blocks, which improves the compiler's ability to find better optimization, improving performance and reducing area by an average of 15 percent. Such a mixed bottom-up, top-down approach is very natural for the designer.

PICO Extreme FPGA extends the collaboration between Xilinx Inc. and Synfora to build a product that can synthesize efficient, multiblock hardware from a C algorithm. By transforming a sequential, untimed C algorithm into highly efficient RTL that meets the performance specifications and is optimized to the target Xilinx device (Spartan-3, Virtex-4 or Virtex-5 FPGAs), PICO Extreme FPGA shields the designer from implementation complexity. This integrates seamlessly with Xilinx ISE design tools and has been designed to take advantage of the embedded DSP and memory features of Xilinx FPGAs without the user having to make any changes to the algorithm. Quality of results has been proven in a series of complex video blocks during Xilinx beta testing.

- Clive Maxfield
Programmable Logic DesignLine

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