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Parallel makes a comeback

Posted: 16 Jun 2008 ?? ?Print Version ?Bookmark and Share

Keywords:ADCs? parallel interfaces? DACs? FPGA? CMOS?

Schweber: Before you know it, we're back to where we were years ago, with large banks of parallel paths, except now clocking at much higher speeds.

Way back in the day, ADCs had simple, parallel interfaces!either TTL or high-level CMOS. Many of these converters could be clocked down to zero samples/s: Once you initiated and they completed a conversion, the result stayed visible, since their parallel output register was static until the next conversion cycle. (DACs had similar, parallel-buffered inputs.)

Old days
From personal experience, I found such static, full-width input eased some of the initial HW/SW debug steps, in those days of crude tools and non-seamless interfaces (so much glue logic!). You could manually check the converter's output with a logic analyzer, scope or even a voltmeter in a crunch.

The large number of IC pins this interface needed was not a big problem in the 8bit and even 10bit resolution world. But as converter resolutions went to 12-, 16-, 18bits and more, the parallel path became part of a package and PCB real-estate problem!both for the converter and for the associated processor!and maintaining signal integrity was also tough. Some vendors went to serial groups of 8bits, in a sort of serialized parallel-interface mode.

Of course, the better answer for today's dense circuitry is a high-speed serial interface, pumping bits out (or taking them in) as a single signal path, sometimes with an associated clock signal. Levels have also changed, going from high-level single-ended to LVDS in many cases.

SI hurdles
Assuming you can support the requisite serial clock rate, the saving in cost due to the smaller die and package, as well as lower board real estate, is significant. Fewer signal lines also simplify PCB track routing and thus the SI challenge.

But even that established I/O standard faces challenges. The JEDEC serial interface standard (JESD204) was ratified in April 2006 and is compatible with many FPGA high-speed interfaces. One vendor, Linear Technology Corp., has announced a 16bit, 80MSps ADC (the LTC2274) that it says is the first to meet this two-wire, 8bit/10bit encoded standard. The serial interface, in conjunction with FPGAs, should result in smaller high-performance systems.

Clocking at higher speeds
But nothing in this business is static. Already, I envision the system designer of an application with a very large number of high-speed channels!such as a specialized detector array in a physics experiment or a high-end MRI scanner!thinking, "Maybe I can use a lot of these converters and FPGAs in parallel, and really get some serious channel count, along with high throughput." Before you know it, we're back to where we were years ago, with large banks of parallel paths, except now clocking at much higher speeds.

As they say, sometimes what's old is new again.

- Bill Schweber
EE Times

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