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IPL Alliance's 'interoperable' ref flow puts pressure on Cadence

Posted: 18 Jun 2008 ?? ?Print Version ?Bookmark and Share

Keywords:EDA market? mixed-signal design? 45nm node? IPL alliance?

The once-sleepy analog EDA market is suddenly generating a buzz, as a number of forces unite to advance the technology and threaten Cadence Design Systems Inc.'s stranglehold.

Ciranova Inc., Magma Design Automation, Synopsys Inc. and others are entering the revived analog EDA fray with tools that compete against Cadence's. However, the biggest jolt for both the market leader and its rivals occurred recently at the Design Automation Conference (DAC), when Taiwan Semiconductor Manufacturing Co. Ltd threw its weight behind a fledgling alliance and announced a major thrust in analog and mixed-signal design.

During the run-up to DAC, silicon foundry giant TSMC joined the Interoperable PDK Libraries (IPL) industry alliance. The IPL group, which includes Magma, Mentor Graphics Corp., Synopsys and other tool and intellectual-property vendors, is pushing for a standard foundry process design kit (PDK). "If and when this technology hits the commercial market, it will function as an "interoperable" reference flow for analog and custom IC design," backers said.

Today's PDKs are proprietary and incompatible. The IPL-backed version is believed to support analog layout tools from all vendors over a common database and to interoperate with Cadence's proprietary analog environment.

However, some view the IPL-backed flow as a competitive threat to Cadence's analog EDA tool suite, dubbed Virtuoso. Cadence has refused to join the IPL alliance, saying the rival technology provides little value for analog designers.

TSMC support
At DAC, the alliance got a shot in the arm when TSMC said it would offer a PDK based on the IPL technology for 65nm and 45nm chip designs in 1H 09. The foundry giant will continue to support Cadence's proprietary analog EDA environment as well. Other foundries and chipmakers are expected to join the bandwagon based on the IPL PDK's promise to reduce costs and accelerate analog/custom IC design.

"Cadence's analog EDA franchise has been broken," said Gary Smith, cofounder and chief analyst with Gary Smith EDA, a market research firm.

"In the past, analog EDA was captive to one supplier, but now the world has opened up for new and competitive tool vendors," said Synopsys CEO and chairman Aart de Geus.

The stakes are high in analog EDA, a $400-million business, according to Gary Smith EDA. Cadence is estimated to own up to an 80 percent share. Some 25 percent of Cadence's total sales are derived from custom IC tools, including analog.

There are still some major challenges in cracking Cadence's dominance. Creating an inoperable PDK sounds good on paper, but the question is whether the stodgy analog world will buy it.

With TSMC backing the IPL alliance, the technology could fly. "One thing is certain, the market is really moving toward mixed signal," said Walden Rhines, chairman and CEO of Mentor. "The digital chip designers are integrating more and more analog" functions on the same chip.

Analog to digital
Several years ago, the digital world embraced tools that were highly automated, thereby boosting the development of complex SoC designs at competitive costs. In contrast, analog design has been stuck in the slow and painful manual world.

In simple terms, designers arrange transistor-level components like capacitors, diodes and the like in a schematic layout. The layout is generated manually via a menu-driven programming function, based on a parameterized-cell (p-cell) methodology. The p-cell libraries include the various transistor-level components.

Cadence's Virtuoso tool suite houses the schematic-layout function, p-cell libraries and simulation tools over the industry-standard OpenAccess database. But Cadence's p-cell libraries are written in a proprietary language called Skill. This locks customers into Virtuoso.

Other EDA vendors sell different schematic-layout packages, bolted on top of the proprietary p-cell libraries for analog design. These tools and Cadence's do not interoperate. "To read the data from one tool to another, designers must use translators, which sometimes cause errors in the design flow," said Tom Quan, deputy director of design services marketing, TSMC.

That's not the only headache in analog. TSMC, for one, generated and maintained 2,500 new and different PDKs in 2007. A PDK consists of several basic elements in the analog/custom IC flow such as schematic symbols and component distributed formats, p-cell libraries, Spice models and technical files.

Each PDK is geared for a particular customer or design, but each kit is also incompatible with the others and expensive.

Taking a step toward interoperable p-cell libraries that can be used with any OpenAccess-based IC layout tool, five EDA vendors last year formed the IPL alliance. They were Applied Wave Research, Ciranova, Silicon Navigator, SpringSoft and Synopsys. Others have since joined, including Helic SA, Jedat, Magma, Mentor, Micro Magic, Virage and, recently TSMC.

P-cell library
The alliance built its open-source, interoperable p-cell library upon Ciranova's PyCell Studio, a free tool that generates PyCells, or "universal" OpenAccess-based p-cells, based on a programming language called Python. PyCell Studio competes with Cadence's technology.

Late last year, the alliance expanded its charter to the development of a "standard" PDK that will operate over the Open-Access database. Ed Lechner, director of product marketing, Synopsys and chairman of IPL, said, "The group has demonstrated a proof-of-concept PDK."

"There are reportedly no bugs with EDA tools that support the OpenAccess database. But there are some issues with Magma's tools, which do not directly read OpenAccess," sources said.

Magma denied those reports as regards to its analog EDA tools, dubbed Titan. "Magma's Titan platform directly reads and writes OpenAccess and does not have any known issues directly reading or writing OpenAcess," said Ashutosh Mauskar, VP of product and business development, custom design business unit at Magma.

The alliance claims to have tested the proof-of-concept library with Cadence's latest Virtuoso 6.1 tool. Nevertheless, it doesn't appear that Cadence will join the group. "I don't see it as a revolutionary step," said Steve Lewis, director of product marketing at Cadence. "We're not sure what the customer will derive from it," he added.

Cadence, however, does see the value of interoperable PDKs. "Industry interoperability is a good thing," Lewis said. "For TSMC, I'm sure it's a noble cause, because they have to do many activities for PDK development."

With regard to analog, the EDA giant is not standing still. Cadence has released a new version of Virtuoso that extends the technology for mixed-signal designs down to the 45nm node.

Rivals' attack
Clearly, Cadence will get a run for its money. At DAC, Synopsys was quietly showing its new, automated analog layout tool, code-named Orion. Prior to that, Ciranova launched Helix, an automated analog layout solution. Helix's primary inputs are a Spice netlist and a PDK containing either Cadence's Skill-based p-cells or Ciranova's PyCells. The output is full device-level placement in either OpenAccess or GDS format.

"Analog and mixed-signal design is the last major EDA market not served by automated layout methods," said Eric Filseth, CEO, Ciranova. "Up to now, the tools simply haven't delivered results acceptable to analog engineers. Helix builds on our proven PyCell technology to enable large and practical productivity gains at the full-circuit level," he added.

Elsewhere, Helic launched a bond wire layout and inductance-modeling tool called VeloceWired. The tool is believed to be suitable in designing analog and mixed-signal ICs, where wire bond inductance may need to be considered as part of the overall component performance.

French EDA startup Infiniscale SA recently launched the TechYielder for yield optimization of complex analog, advanced mixed-signal and RF blocks designed with sub-90nm design kits.

- Mark LaPedus
EE Times





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