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Taking advantange of page mode read on the MCF5407 Coldfire

Posted: 25 Jun 2008 ?? ?Print Version ?Bookmark and Share

Keywords:page mode read? flash memory? page access?

Spansion LLC offers a class of flash memory devices that dramatically reduce read access time. Devices such as the S29GLxxxN family of flash devices (including the S29GL512N, S29GL256N, and the S29GL128N) have a read page mode with a 25ns access time. This is a 65-ns reduction from the standard read-access mode of 90ns.

Page access is faster because the data is read from an internal register instead of directly from the memory array. During a standard read access, the flash device stores a group of adjacent words, referred to as a page, into an internal register bank. A page is eight 16-bit words. The lower two address bits select the individual word within a page. The upper address bits (A[MAX:3]) represent the page address and A[2:0] represent the intra-page address. A new page is selected every time the page address changes or CE# toggles HIGH then LOW. Note, if the device is in the byte mode (BYTE# = 0), the page address is A[2:0], A-1. The page size when the device is in the byte mode is 16 bytes. Refer to the S29GLxxxN data sheet for more information on the byte mode.

To take advantage of page operation, the system must provide logic that accommodates page address boundaries and the difference in access time between the initial access and subsequent page accesses.

The Coldfire MCF5407UM processor already has such logic integrated into its memory interface. Whenever possible the processor performs a burst access of up to four line bursts. It is capable of 2-1-1-1 line bursts. The first access requires two processor clocks, while each of the three subsequent accesses only require a single processor clock. Wait states can be added externally by holding off the assertion of Transfer Acknowledge (TA#).

View the PDF document for more information.

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