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Lattice IP cores aim at wireless base stations

Posted: 27 Jun 2008 ?? ?Print Version ?Bookmark and Share

Keywords:IP core? intellectual property? wireless communications? Ethernet?

The folks at Lattice Semiconductor have announced the availability of three new intellectual property (IP) core and reference design products targeting the wireless communications market. The products include RF/IF processing functionality, as well as upgraded support for industry-standard base station connectivity protocols. The designs are optimized to run on the LatticeECP2M FPGA family in order to provide complete, low cost wireless base station solutions.

The three designs being released include a digital up/down conversion reference design (DDC/DUC) and IP cores supporting two popular industry standard baseband interface protocols, the Open Base Station Architecture Initiative (OBSAI-RP3-01) and the Common Public Radio Interface (CPRI). The DDC/DUC is a single channel, WiMAX reference design that leverages the embedded DSP blocks of the LatticeECP2M fabric to provide a highly integrated RF card solution. The DUC/DDC package also automatically configures the Lattice ispLeverCORE IP cores for the Finite Input Response (FIR) filter and Numerically Controlled Oscillator (NCO) functions.

Both the CPRI and OBSAI IP cores have been recently updated to address the expanding landscape of remote radio head base station deployments. The CPRI core is compliant with v3.0 of the specification, supporting 614M, 1.2G and 2.4Gbit/s data rates by virtue of the embedded Serdes channels in the LatticeECP2M FPGA family. The IP core also has been upgraded to address the concerns of latency variation and enhanced Fast C&M Ethernet control plane requirements that are required for multi-hop remote topologies.

The OBSAI core has been updated to support v4.0 of the specification, which adds a protocol overlay called RP3-01 to the preceding version in order to address the needs of a remote base station topology. Enhancements to the Transport Layer include support for the mapping of RP1 control plane data into an RP3 message, reducing connectivity by allowing both data and control plane messaging to be delivered over a common RP3 electrical link. Also offered is a unique mux/demux capability that further aids in the aggregation and distribution of multiple OBSAI links. Lattice offers development boards and demonstrations to further aid in the design cycle process.

These newly announced cores complement other recently announced Lattice products in the wireless solutions segment that include an LTE compliant Turbo Encoder/Decoder from TurboConcept, a jointly developed solution with Linear Technology supporting high speed serial connectivity (JESD204) for ADCs and support for a Serial RapidIO end point core developed by Praesum Communications.

- Clive Maxfield
Programmable Logic DesignLine

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