FAN5109 V_CC bypass considerations to reduce voltage spikes

The use of smaller semiconductor geometries results in faster switching times. It is well-known in the industry that the lower switching losses allow for higher frequency operation. This doesn锟絫 come without penalty, however, since faster switching times also result in larger voltage spikes due to the parasitic inductance and capacitance of the board layout and component packaging. As switching times decrease, experienced power supply designers take greater care to minimize output transistor voltage spikes that are generated in the end product.

Few people, however, realize that the geometries of other power components in today锟絪 designs are also decreasing, making them fast enough that their voltage spikes also need to be considered to ensure reliable, robust designs. An example is the latest breed of driver circuits.

The focus of this document is to understand and mitigate V_CC spikes when using the new FAN5109 driver.

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