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Altera tool builds DSP design in minutes

Posted: 02 Jul 2008 ?? ?Print Version ?Bookmark and Share

Keywords:high-performance DSP designs? Simulink design? model-based synthesis?

Targeting high-performance DSP designs, Altera Corp. rolled its DSP Builder tool version 8.0, featuring second-generation model-based synthesis technology. This technology allows DSP designers for the first time to generate automatically timing-optimized RTL code based on high-level Simulink design descriptions. With this new DSP Builder feature, designers can achieve high-performance design implementations, running at near-peak FPGA performance, in a matter of minutes. This is a significant productivity savings compared to the hours, if not days, required to hand-optimize HDL code.

"DSP Builder's second-generation model-based synthesis technology allows customers to use Simulink as the modeling, simulation and implementation environment of choice for high-performance DSP designs," said Ken Karnofsky, marketing director for signal processing and communications at The MathWorks. "This technology allows designers to vastly improve their productivity as they implement DSP functionality on Altera's FPGAs."

Designing multichannel signal processing data paths in applications such as multicarrier, multi-antenna RF processing in wireless basestations, the new DSP Builder second-generation synthesis technology delivers dramatic productivity gains. The DSP Builder tool automatically adds pipelined stages and registers, and implements time division multiplexing to generate highly optimized designs for functions such as digital upconversion (DUC), downcoversion (DDC), crest factor reduction (CFR) and digital predistortion (DPD). This greatly enhances productivity and enables users to perform system level design exploration rapidly, and to easily scale their design for varying carrier bandwidths, number of carriers, antennas, and sectors. DSP Builder version 8.0 includes design examples for multi-antenna, multi-carrier WiMAX and W-CDMA DUC and DDC designs.

"Altera continues to set the standard for FPGA design productivity, including high-performance DSP designs," said Chris Balough, marketing director for software, embedded, and DSP at Altera. "The innovative synthesis technology included in DSP Builder version 8.0 delivers a timing-driven FPGA implementation environment that allows designers to get the system performance they require with the push of a buttonenabling an order-of-magnitude productivity gain."

Used with Altera's Quartus II design software, DSP Builder version 8.0 is available now for purchase.





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