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Interconnect links processing, memory channels

Posted: 04 Jul 2008 ?? ?Print Version ?Bookmark and Share

Keywords:multiple memory channels? chip-level interconnect?

Sonics Inc. rolls out a new chip-level interconnect technology, addressing what it says is a growing memory bandwidth problem faced by a broad range of people who develop video processors. SonicsSX can intelligently connect multiple processing elements on a chip with multiple channels of external memory.

As systems move into the era of high-definition video, an increasing group of ASIC designs are starved for memory, said Drew Wingard, chief technology officer of Sonics, a 12-year-old interconnect specialist. Consumer giant Philips recently wrote a white paper suggesting memory bandwidth requirements for video designs have increased seven-fold, he said.

The problems are being felt not only by designers of ASICs for STBs, HDTVs and videogame consoles. "Some vendors pushing the edge of chips for smart phones are feeling this, and chip makers targeting video cameras and media players will feel this in a year or two as well," Wingard said.

The shift to DDR3 DRAMs helps but does not eliminate the bandwidth problem. In part, that's because many commonly used processor cores and accelerators are typically limited to transferring 32bit chunks of video data at a time, he said.

"We need to move to support for multiple memory channels," said Wingard.

SonicsSX address the problem with several advances over the company's existing chip-level interconnects. The new offering expands the maximum bus width from 128bits to 256bits, it increases throughput from 6- to 16Gbytes, and most importantly in shifts from support of one to as many as eight memory channels.

"The biggest challenging with multichannel memory is load balancing," said Wingard.

Sonics has developed interleaving techniques that are flexible and optimized to the operations of underlying memory and controller chips. SonicsSX also implements new data structures to improve the efficiency with which the interconnect grabs related pixel data and addresses.

The interconnect aims to replace proprietary solutions individual SoC designers are creating on an ad hoc basis for each new ASIC they develop. Engineers could use existing on-chip links such as an ARM Ltd. AXI bus to implement multichannel memory, but it would require adding new buffers to handle data about out-of-order transactions, potentially adding 20-50 percent to the silicon cost of the interconnect, Wingard said.

Sonics charges an upfront licensing fee and per-chip royalty for using its interconnects. SonicsSX represents a new high-end product for the company. Thus Sonics will charge a premium for the technology. Wingard would not quote pricing which is based on individual negotiations.

- Rick Merritt
EE Times

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