High-density coprocessor module delivers 'fastest' connection
Keywords:FPGA? FSB module? multiprocessor? servers?
The XD2000i family offers the highest density Stratix III FPGAs in the smallest footprint available in the market. The module uses three FPGAs, one as a bridge to system resources in Intel Xeon processor-based servers, leaving the other two to run user applications found in military, financial, medical and bioscience markets.
The coprocessor modules substantially accelerate applications via parallelization and pipelining, while simultaneously reducing overall system power consumption and latency. In the Stratix III FPGA-based FSB module, 4x acceleration is expected when running the Monte Carlo Black-Scholes algorithm in double-precision floating point when compared to RapidMind's GPU single-precision results published earlier this year for one million paths per option. The XD2000i module is also believed to enjoy power, space and memory error correction coding advantages over current GPUs: power is sub-60W and the module can be packed densely into a blade form factor. The FPGA coprocessing solution opens up a number of new opportunities in markets where Intel-based servers are presently being used.
Customer's satisfaction
The combination of an Intel Xeon 5000 series processor and a Stratix III FPGA coprocessor in the XD2000i module are claimed to provide customers with the highest performance FSB accelerator available while delivering significant cost, power and space savings.
Intel is enabling tightly coupled, in-socket, FPGA-based accelerators. Placing the Stratix III FPGA-based XD2000i in one of the Intel Xeon processor sockets gives the coprocessor a high-speed link to memory, as well as a fast connection to the host processor, without requiring board modifications, thus providing designers with a simple hardware integration path. A new version of the XD2000i module will be available in the Q3 2008 that will work with quad socket boards to provide over 500K logic elements and 1,536 multipliers with separate FSB processor interconnect.
- Clive Maxfield
Programmable Logic DesignLine
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