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Memory tester offers improved efficiency

Posted: 11 Jul 2008 ?? ?Print Version ?Bookmark and Share

Keywords:memory? tester? Flash technology? scalability?

Teradyne Inc. has expanded its family of Magnum memory test systems with the launch of Magnum II, which delivers higher speeds and performance requirements for flash and embedded memory systems. "This memory tester is based on the Magnum I architecture that sets the standard for low-cost production test capacity, while adding eight times the performance for leading-edge Flash technology," Teradyne said.

Magnum II expands performance for both bandwidth and test efficiency. The memory tester provides a 400MHz clock and data rate, with capability up to 800Mbit/s data rate in SuperMux mode, without any loss of resources.

The Magnum II's Algorithmic Pattern Generator has been enhanced to improve its scalability and throughput efficiency and supports the testing of Terabyte scale memories. In addition, the error capture and redundancy analysis circuits have been optimized to capture up to 5760Gbit of error information per system, at-speed, with redundancy processing in the background. "Test times can be reduced significantly while running at the full device speed," Teradyne said.

Magnum II also delivers an extended logic capability that supports up to 512mV per pin, four times the vector depth of Magnum I, with no shared pins. Magnum II supports independent data per pin for flexible testing of high-speed devices. It is compatible with Magnum I signal delivery when interfacing to a number of handler and prober systems, enabling customers to reuse their existing interface products for massively parallel test applications.

- Gina Roos

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