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New XAP processor is built for Zigbee, Bluetooth

Posted: 14 Jul 2008 ?? ?Print Version ?Bookmark and Share

Keywords:16bit processors? flash memory? wireless networks?

Cambridge Consultants has devised a new architecture for the latest version of its core for 16bit processors, the XAP5 that includes special features for running programs held in on- or off-chip flash memory.

The company says the fifth variant of its XAP core offers advanced computing functionality at the lowest unit cost and lowest power.

The XAP5 is said to combine the economy of a 16bit data word with a 24bit address space for large programs up to 16Mbytes, which suits devices designed for data-centric communications applications in markets such as consumer, industrial and retail.

Target applications include Zigbee and Bluetooth wireless networks, energy metering, sensor networks, tagging and transactions using RFID or NFC, location systems such as GPS and other embedded ASIC application that requires a robust and capable software environment.

"Non-volatile flash and OTP memory has had a huge impact on chip design for such applications, and this latest version of the XAP processor core was developed to meet this need," said Alistair Morfey, technology director at Cambridge Consultants and chief architect of the XAP range.

"The XAP5's design benefits from our own experience of the ASIC requirements for portable wireless, sensing and medical devices. We have focused our architecture on the memory architectures typically found in such ASICs. Reducing unit cost and power consumption for sophisticated software applications have been the primary goals."

The XAP range of processor cores, development of which goes back to the 1990s, is already embedded in over 1 billion chips worldwide, added Morfey.

Like its predecessors, the XAP5 processor core is delivered as a soft IP core in Verilog RTL that licensees design into ASICs and can synthesize to FPGA for verification.

Morfey says the core includes exceptionally high code density due to careful instruction set design. The processors use mixed 16bit, 32bit and 48bit instructions, with the linker automatically choosing the shortest form of instructions set. This minimizes the size and cost of program memory, high performance (68 Dhrystone MIPS when clocking at 100MHz on a 0.13?m CMOS process) and a small footprint of 18, 000 gates.

The 0.68 DMIPS/MHz is achieved when executing in-place from 16bit memory, and is said to be as good as popular 32bit processors in their 16bit mode.

The processor core also features protected software operating modes that partition user and privileged code for secure, high-availability applications. The processor hardware is supplemented by software and development tools architecture, including a GNU C compiler and assembler, which support a sophisticated programming environment. XAP5 is supported by iXDE, and SIF development and debug tools.

For example, the XAP5 supports in-place execution of programs that can be located anywhere in memory without the need for linking or copying them to different locations. This means programs can be easily distributed and will start up faster. It also offers a robust update of programs stored in flash without the risk of losing the system partway through the update process.

The first company to have deployed the XPA5 core is Dutch wireless chip group Greenpeak Technologies for its sensor network ASIC.

"A lot of other companies are also evaluating the core, for instance for use in embedded sensors and wireless sensors, and we are using the technology in numerous projects within Cambridge Consultants' ASIC projects targeting applications such as energy control and smart metering, medical and wireless communications," Morfey told EE Times Europe.

- John Walko
EE Times Europe

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