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High-voltage I/O library integrates ESD protection

Posted: 15 Jul 2008 ?? ?Print Version ?Bookmark and Share

Keywords:high-voltage CMOS process? ESD protection? high-voltage I/O library? floating logic?

austriamicrosystems business unit Full Service Foundry announced that its state-of-the art 0.35?m high-voltage CMOS process technology "H35" is now offering 4kV ESD protection. The silicon-proven H35 periphery library guarantees a 4kV HBM (human body model) ESD protection compliant to the MIL-883E, Method 3015.7 and Jedec JESD22-A114B ESD standards.

The I/O library cells with built-in ESD protection structures offer 4kV HBM ESD protection level for 50V maximum supply voltage and are available as an add-on to the current HIT-Kit version v3.72. Registered users may download the new periphery cells from the company's technical Web server.

"Proper ESD protection on both chip and system level is one of the utmost demands of our customers. Offering competitive ESD protection solutions enables us to serve our customers' needs and demands in designing complex analog mixed-signal products with optimal ESD protection on chip level," says Thomas Riener, general manager of full service foundry at austriamicrosystems. "Dedicated ESD reviews and consulting services further enhance austriamicrosystems' analog foundry portfolio."

austriamicrosystems' 0.35?m high-voltage CMOS technology is said to be the first purely CMOS based high-voltage process that matches BCD performance and chip sizes at much lower process complexity. It offers fully scalable High-Voltage NMOS and PMOS devices, floating logic libraries as well as a best-in-class power-on resistance. The process allows the integration of 3.3V, 5V, 20V, 50V and 120V devices on a single chip, which makes it a suitable technology for complex analog, mixed-signal designs in power management, automotive or medical applications.





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