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Two design IP cores simplify interface connection

Posted: 22 Jul 2008 ?? ?Print Version ?Bookmark and Share

Keywords:IP cores? processor? FPGA? ASIC?

eInfochips Ltd has launched two design IP cores designed to reduce networking interfaces and video surveillance chip development time and cost.

The new IP cores emerged a month after the company announced verification cores. They will supplement an increasing portfolio of high-speed bus protocol and video processor cores.

The new IP cores comply with the Optical Internetworking Forum's SPI4.2 design IP (System Packet Interface Level 4, Phase 2) and other ITU specifications. eInfochips claimed the SPI4.2 design IP is a configurable implementation for high-speed networking interfaces where queuing, scheduling, arbitration and credit management are handled outside the SPI 4.2 IP core.

The CCIR656 design IP provides a video interface for display controller ICs and supports 525-line and 625-line interlaced TV displays used for digital surveillance systems, digital cameras and advanced mobile phones with video capabilities. "It can be implemented on an FPGA or ASIC," the company said.

"The cores include verified RTL code (Verilog), synthesis scripts, timing constraints and design specs," said Nirav Shah, marketing director, DisplaySearch.

- K.C. Krishnadas
EE Times

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