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EUV delays drive shift to double-patterning

Posted: 22 Jul 2008 ?? ?Print Version ?Bookmark and Share

Keywords:lithography? EUV litho? double-patterning? extreme ultraviolet?

With the probable delays for extreme ultraviolet (EUV) lithography, ASML Holding NV, Canon Inc. and Nikon Corp. are racing each other to capitalize on the shift towards double-patterning technology at the 32nm node and beyond.

ASML and Canon have expanded their respective scanner lineups, while Nikon tweaked its road map, as chipmakers rethink their double-patterning strategies. But at this week's Semicon West, IMEC and JSR Corp. may have stolen the show by rolling out a new "freezing" technique in double-patterning lithography. The entities claimed to have found a simplified process using only one etch step to reduce the cost of double patterning.

Double-patterning shift
The industry is gearing up for double-patterning!and for good reason: There are ongoing rumors that EUV will not be ready for the 22nm node, meaning the technology has been pushed out to the 16nm node or beyond. This also implies that chip makers may have to resort to 193nm immersion lithography!with double-patterning techniques!for both the 32- and 22nm nodes.

Double-patterning implies that the wafer must be exposed twice, thereby increasing lithography costs. Even within the double-patterning world, there are various and complex flavors of the technology: double-exposure; trench double-patterning; line double-patterning; litho-etch-litho-etch, spacer and others.

Each technology has its own set of trade-offs. The biggest concerns with double-patterning are cost and overlay, said Harry Levinson, manager of strategic lithography technology and fellow at Advanced Micro Devices Inc.

The DRAM, NAND flash and logic camps will continue to use single-exposure techniques for current-generation devices!until, say, the 45nm node and perhaps beyond.

At the 3x node or perhaps before that, the NAND flash-memory crowd, which is pushing the leading-edge, is looking at using 193nm immersion lithography!with a technology called "spacer" or self-aligned double-patterning. Some NAND flash players are already using this technology, reportedly including Hynix Semiconductor Inc. and IM Flash Technologies LLC, the Intel-Micron memory venture.

In the past, the DRAM camp was looking at the so-called litho-etch-litho-etch scheme. Now, the DRAM camp is reportedly ditching this scheme in favor of the spacer technology.

The logic crowd wants to avoid using double-patterning techniques, although that might be easier said than done in most cases. Logic chipmakers may be able to push out double-patterning by restricting their design rules.

Nikon's plan
In any case, Nikon Corp. tweaked its road map. Earlier this year, the company disclosed that it is developing two 193nm immersion scanners for double-patterning applications, including the S611C and S620D.

The S611C was an early "learning tool" that was supposed to be shipped by year's end, according to Nikon. Nikon will not field the S611C. Instead, the company will integrate many of the features of the S611C in its current 193nm immersion tool, dubbed the S610C.

The S620D is still on track. The machine is geared for 45- and 32nm designs and is said to have a throughput of 180 wafers per hour. It is expected to be delivered in 2009.

Immersion litho
At Semicon, ASML Holding NV announced it has developed another model of lithography equipment, the Twinscan XT:1950i. The tool is said to increase the performance of 193nm immersion lithography by 25 percent.

The new tool is a souped-up version of its current system, the 1900i. The XT:1950i system offers improved overlay, resolution and throughput, to enable high-volume manufacturing of 38nm memories and 32nm logic semiconductors using a single exposure, ASML said.

The XT:1950i is the industry's first single-exposure immersion lithography system for high volume manufacturing at 38nm, a shrink that makes 10 percent more wafer area available for chips over the XT:1900i, ASML said. In addition the XT:1950i offers a productivity of 148 wafers per hour, an increase of 15 percent from previous Twinscan models.

On its previous roadmaps, ASML has talked about a new tool for the double-patterning era. Robert Socha, an ASML fellow, said the company is working on a new tool that will bring the overlay down to 2nm.

Late last year, Canon quietly entered the 193nm immersion lithography market. The company has been ramping up its new AS7 tool in the marketplace.

The AS7 has a field size of 26mm x 33mm and a numerical aperture of 1.35. The two-stage system has demonstrated images down to 40nm with a k1 factor of 0.280 and 37nm with a k1 factor of 0.259.

On its road map for 2009, Canon is expected to ship a 193nm immersion tool, which is geared for double-patterning applications. Target throughput is 200 wafers an hour.

Freezing technique
Meanwhile, at Semicon, IMEC, in collaboration with JSR, claimed a breakthrough in the double-patterning arena. When using two lithography and two etch steps!or the so-called litho-etch-litho-etch process!this technique will be expensive and slow, according to IMEC and JSR.

IMEC and JSR propose another approach. Both 32nm lines and spaces were printed with a double exposure/single etch process, effectively freezing the resist after the first exposure. This simplified process paves the way for double patterning for the 32nm technology node, according to the entities.

The freezing material used to reach this result has been developed by JSR. "It prevents the resist from expanding or shrinking. And when the second resist layer is added, the two do not interact. Also, the freezing material is compatible with the lithography hardware," according to IMEC and JSR.

The step of freezing the resist is done in a wafer track. After exposing the first pattern, the resist is coated with the freezing material. Next, the wafer is baked to freeze the resist. Then the excess freezing material is removed using a developer.

In the following step, a second resist layer is added and the second exposure is done. To prevent the second resist layer solvent from washing away the first resist, the freezing material changes the properties of the first resist layer so that it becomes non-soluble in the second resist layer.

This technique allows printing 32nm dense lines using dipole illumination at 1.0 NA. CD uniformity for the 44nm "half-pitch" lines was 3Σ = 2.4nm.

Within its R&D operations, IMEC is currently transferring this process to ASML's XT:1900i line of 193nm immersion lithography tools. The technology will be used to explore wafer processing at the 32nm node and beyond.

- Mark LaPedus
EE Times





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