Project Galaxy allots $6.4M for GALS research

The EU-funded Project Galaxy has started developing a design process for globally asynchronous, locally synchronous (GALS) architecture chips with novel network-on-chip (NoC) capabilities.

Arteris Inc., originally a French company, operates commercially in this area. It recently relocated its headquarters to California.

Project Galaxy (GALS Interface for Complex Digital System Integration), which started in June, is funded under the European Union's Seventh Framework Program (2007-2013). A consortium, led by research institute IHP GmbH, is carrying out the $6.4 million project. About $4.6 million of the budget is being provided by European taxpayer through the offices of the European Commission and the rest by the project partners including the University of Manchester, University of Bologna, EPFL, Silistix Ltd and Infineon Technologies AG.

The project is intended to evaluate the ability of the GALS approach to solve system integration issues. The results will be demonstrated by implementing a complex wireless communication system.

The increased complexity, performance requirements, and the need for power and EMI reduction are big challenges for designers of complex chips. Furthermore, the continued technology improvement towards nanoscale dimensions brings additional challenges for embedded system design. For that reason, chip designers and system engineers have recognized the necessity to deal with these issues; one very promising option is the use of a GALS design methodology.

Most of the today's designs are synchronous, i.e. there is a common clock signal driving all blocks in the design. However, it is possible that system blocks internally operate synchronously and communicate asynchronously. In this case, there is no need for a common clock that should synchronize all blocks. Such system is usually referred to as a GALS system.

The goal is to promote the development of GALS system design by providing an interoperability framework between existing open or commercial CAD tools.

It is planned to explore and evaluate the ability of GALS to solve system integration issues as well as building on its reduced EMI and low-power properties. A promising target platform can be seen in the area of NoCs. In this project, different approaches of implementing GALS-enabled NoC platforms will be investigated and compared with fully synchronous implementations. The NoC design flow will be integrated into the GALS design flow.

"The project reinforces European competitiveness by extending the existing expertise in synchronous and asynchronous design methodologies in the direction of heterogeneous design methods. The GALS technique will play a major role as the integration technique for future complex embedded systems," said project coordinator Milos Krstic from IHP.

- Peter Clarke
EE Times Europe