Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Embedded

XPLA3 I/O cell characteristics

Posted: 24 Jul 2008 ?? ?Print Version ?Bookmark and Share

Keywords:XPLA3 I/O cell? EMI? XPLA CPLDs? impedance?

The I/O cell architecture used in XPLA3 CPLDs is intended to give designers maximum control and flexibility when implementing their designs. Each I/O cell can be implemented in one of several different modes such as a high impedance input, input with weak pull-up, output, bidirectional, or unused pin without the need for external termination. The specific I/O cell function implemented is supervised by a set of internally generated control signals.

XPLA3 I/O cells have several other beneficial features such as PCI compatibility, ability to sink and source up to 8mA, "hot plugging" capability, half latch and 5V tolerance. Additionally, the XPLA3 I/O cells have a slew rate control option for each macrocell, which can be used to reduce reflections and EMI.

This paper describes the features and benefits of the I/O cells provided by Xilinx CoolRunner XPLA CPLDs.

View the PDF document for more information.

Article Comments - XPLA3 I/O cell characteristics
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top