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Maximize switcher efficiency, minimize size

Posted: 01 Aug 2008 ?? ?Print Version ?Bookmark and Share

Keywords:switch? FET? IC? layout? current?

Today's switching regulators and supplies are more compact and powerful. However, one of their major tradeoffs is a higher switching frequency, which makes board design all the more difficult. The board layout more than ever differentiates a good switcher design from a bad one. Here are some tips on how to create a good board layout.

The simplified circuit diagram in Figure 1 is necessary in understanding the process. Observe the current paths. Mark the ones in red that apply to the FET in its "on" state, and mark the ones for the FET in its "off" state with a green pencil. We can see two different scenarios such as areas of two colors and areas with only one color. We must pay special attention to the latter condition because in there the current alternates between zero and full value. Those are the areas with a high di/dt.

Alternating currents with high di/dt generate a significant magnetic field around the PCB traces. This is a major source for interference in other parts of the circuit and other circuits on the same or adjacent boards. Common current paths are less critical assuming it's not an alternating current, and thus the effects of di/dt will be much less. Meanwhile, those areas carry a higher load over time. In this example, common paths exist from the diode's cathode to the output and from output ground to the anode of the diode. The output capacitor shows extremely high di/dt as the capacitor charges and discharges. The traces to and from the output capacitors have to fulfill two conditions. They need to be wide because of the high current, and as short as possible to reduce di/dt effects.

In practice, the designer wouldn't implement a traditional layout with traces running from Vout and ground to the capacitor. Those traces will be the ones carrying high-alternating currents, which is a better way to connect the output and ground directly to the terminals of the capacitor. Thus, alternating changing currents are only found at the capacitor. The remaining traces to the capacitor will now carry an almost constant current flow, and any problems with di/dt will be solved.

Current alternates between zero and full value in the areas with only one color. These areas have high di/dt.

Simply placing a groundplane in "level 2" and connecting all ground connections to it will not show good results. Let's find out why. Our design example has currents of up to 3A that have to flow through ground back to the source (a 24V car battery or a 24V power supply). The diode, COUT, CIN and the load have high current at their ground connections. The ground connection of the switching regulator carries little current. The same is true for the ground reference of the resistive divider. If all the ground pins are connected to a ground plane, we would get ground bouncing. Although small, the sensitive points in the circuit (such as the resistive divider that derives feedback voltage) will not see a stable reference ground. Thus, overall regulation accuracy will suffer greatly. We could even get ringing from the source hidden within the groundplane on level 2, which is hard to locate.

In addition, the high-current connections would have to use vias to the groundplane, another source of interference and noise. A much better solution uses the ground connection of CIN as a star point for all high current ground traces on the input as well as on the output side of the circuit. This star point is connected to the groundplane, as well as the two low-current ground connections (IC and divider).

Now, the groundplane will be clean: no high current, no bouncing. All high-current grounds are star-connected to CIN ground. What the designer has to do is make the ground traces (all on the top level of the board) as wide and short as possible. In this context, saving copper per se has never shown good results.

Impedance of the nodes
The nodes to check are the high-impedance ones, as they can easily catch interference. The most critical node is the feedback pin of the IC, which receives its signal from the resistive divider. The FB pin is the input of an amplifier (like the LM25576) or a comparator (as is the case with hysteretic regulators). In both cases, the FB point has quite high impedance. Accordingly, the resistive divider should be located right at the FB pin, with a short trace from the center of the divider to FB. The trace from the output to the divider is low impedance and can be routed to the divider in some longer trace. The length of this trace is not critical, but the routing is.

Other nodes, however, are not so critical. No need to worry about the switching node, diode, COUT, the VIN pin of the switcher IC or CIN.

Resistive divider
Routing makes a difference for the resistive divider. This trace goes from COUT to the divider and its ground back to COUT. We have to make sure that this loop does not form an open area. Open areas can act like receiving antennas. If we can make sure that the groundplane below the trace is undisturbed, then the area made up by the trace and ground below it and the distance between level 1 and level 2 should be clean from interference. Now, it becomes clear why ground should not be on level 4. The distance would be significantly increased.

Alternatively, the ground connection of the resistive divider could be routed on level 1, with both traces in parallel and as close together as possible to keep the area small. These observations apply to all traces that carry signals like sensor connections, amplifier outputs, ADC inputs or audio amplifiers. Every analog signal should be treated in a way to reduce the capability to pick up any noise.

Smaller is better
Reducing open board areas whenever possible also holds true for low-impedance traces. We have in this case a source "antenna" for potentially transmitting interfering signals to other sections of the board or device. Again, smaller is better when it comes to open board areas.

Two other critical traces include the one from the switching output of the IC to the node of the diode and inductor, and the trace from the diode to this node. Both traces carry high di/dt, either the switch is on or the diode carries current, and so the traces need to be as wide and as short as possible. The trace from this node to the inductor, and from the inductor to COUT, is less critical. In this case, the inductor current is relatively constant and changes slowly. All we have to do is make sure it is a low-impedance point to minimize voltage drop.

Shown is an example of a good PCB layout for a switcher. Note that the ground point of the capacitor is directly connected to the anode of the diode.

Workable layout
Let's take a look at an example of a good layout, as shown in Figure 2. The main component of a good layout is a controller in an MSOP-8 package, used in relation to an external FET. Observe the area of CIN. Notice that the ground point of this capacitor is directly connected to the anode of the diode. You cannot make the trace in "power ground" much shorter. The FET [SW] could be moved a few millimeters up to shorten the cathode-inductor-FET trace.

The area of COUT is not visible, but we can observe that the resistive divider (FB1-FB2) is very close to the IC. FB2 is grounded to a separate ground plane, and so is the ground pin of the IC. The "signal" ground is connected to the groundplane using three vias, the same as for the "power" ground connected at the GND pin of the board. Through this, "signal" ground cannot see any bouncing that occurs on the "power" ground.

If you apply a few simple rulesonly some of them have been discussed herethe bard layout will be virtually free of trouble.

Spend the time to really think about board layout before you lay it outit'll save you time later in trying to cure some obscure behavior in your switching power supply.

- Juergen Kuehnel
Technical Trainer
National Semiconductor GmbH

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