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Libero IDE loads new power reduction options

Posted: 07 Aug 2008 ?? ?Print Version ?Bookmark and Share

Keywords:power supply? power reduction? FPGA IDE?

Actel Corp. has introduced new power reduction and design creation enhancements to their Libero Integrated Development Environment (IDE).

Giving designers additional power supply options and enabling even lower power consumption, the new Libero IDE 8.4 offers an FPGA core operating voltage range from 1.14V to 1.575V for its flash-based IGLOO, IGLOO PLUS and ProASIC 3L FPGAs.

Enhancements to the SmartPower analysis tools within the Libero IDE also allow easy comparisons of multiple design scenarios and their resulting power consumption and battery life implications. For rapid and efficient design creation, the Libero IDE 8.4 also allows Actel-created or third-party intellectual property (IP) blocks, user-developed HDL modules, and glue logic functions to be easily combined in an accessible project area.

"In a market sensitive to power consumption and design cycle time, we know that software tools are critical to the success of the project," said Fred Wickersham, senior marketing manager for Actel software tools. "For simple low-power designs or sophisticated processor-based SoC solutions, the new Libero IDE 8.4 dramatically simplifies the design process with easy-to-use tools that identify and reduce sources of power consumption within a design; remove tedious design tasks like writing new HDL code for logic functions; and make connections between the myriad functions on the FPGA or externally."

Libero IDE enhancements
The Libero IDE 8.4's enhanced SmartPower analysis tool suite allows users can create and compare multiple user-defined power profile "scenarios," enabling them to test operating options to better determine the best design approach for their power-sensitive application.

Offering users improved ease of use as well as a comprehensive understanding of power usage in all functional modes of the design, SmartPower also offers new graphical power consumption displays.

Conventional design methodologies include ground-up generation of HDL code or schematic designs to create and stitch the necessary combination of logic functions that make up the FPGA system or sub-system. The improvements to SmartDesign within Libero IDE 8.4 allows users to import user- or third-party created HDL modules, IP, and glue-logic functions into the project area. The user is then able to quickly select the desired blocks from among the imported functions or the existing catalog of IP cores and drop them onto an enhanced white board-like 'canvas' where they are viewed and connected in a system block diagram. In the end, a design rule checked and synthesis-ready HDL file is created. SmartDesign supports the quick building of simple designs or sophisticated complex processor-based SoC solutions.

The Actel Libero IDE Gold edition is available on Windows free of charge. The Actel Libero IDE 8.4 Platinum edition is available now on Windows and Linux platforms for $2495. All editions are one-year renewable licenses.

- Clive Maxfield
Programmable Logic DesignLine





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