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45nm structured ASICs boast zero mask charge

Posted: 07 Aug 2008 ?? ?Print Version ?Bookmark and Share

Keywords:zero mask charge? structured ASIC? 45nm node? FPGA?

The last few years have observed a huge slide of worldwide ASIC design starts. Leading-edge ASIC design costs have risen to the point where many small- to medium-sized companies have no choice but to use FPGAs.

Unfortunately, FPGAs can't achieve the low-power consumption and extreme performance offered by ASIC technologies. One answer is the use of structured ASICs, in which most of the device is pre-fabricated and the device is customized using only the metallization layers. Due to the sophistication of the underlying structured ASIC fabric, the majority of the metallization layers are also predefined.

Of course, not all structured ASIC technologies are created equal. Many structured ASIC architectures require the customization of two or three metallization layers, which still involves a substantial amount of cost. Furthermore, creating custom tracking layers dramatically increases the complexity of the design process, because now you have signal integrity issues to worry about.

By comparison, some structured ASIC fabrics require the customization of only a single via layer, which significantly reduces costs and design complexity. Such is the case with the Nextreme structured ASIC products from eASIC. Furthermore, this via layer can be implemented using direct-write electron beam, thereby eliminating the need for any custom mask charges, which is why eASIC refers to these devices as "zero mask-charge ASICs."

45nm structured ASIC
The folks at eASIC are obviously doing something right, because they've had 120 design wins with their 90nm Nextreme structured ASIC family. Leveraging this success, they've just announced their next generation, 45nm Nextreme-2 Family of devices.

The Nextreme-2 Family delivers on eASIC's promise of affordable silicon customization, enabling the design of custom chips using 45nm technology and the delivery of working devices in only six-weeks. eASIC is currently engaged with early access customers and mainstream availability will commence in Q4.

The no-minimum order quantity Nextreme-2 ASIC family paves the way for accelerating eASIC's market expansion into the $85 billion global logic market, the worldwide semiconductor industry's largest sector.

A brief summary of the Nextreme-2 family's features and capabilities is as follows:

  • Up to 80 percent lower power than FPGAs
  • Up to 20M gates
  • Up to 30Mbit of true dual-port memory
  • Up to 2.4 TeraMACs of DSP performance
  • Up to 5.6-, 6.5Gbit/s transceivers and 1.25Gbit/s LVDS
  • Simple design tools and flow
  • Six weeks to silicon devices
  • No minimum order quantity

    The Nextreme-2 Family is manufactured on Chartered Semiconductor's 45nm low-power (LP) process and armed with the industry's most efficient LUT-based architecture.

    The logic fabric provides up to 700MHz performance enabling signal processing engineers with 2.4 TeraMACs of DSP capability without the need for embedded multipliers.

    The combination of triple oxide transistors, 45nm LP process and eASIC's patented power-management architecture enables Nextreme-2 to lower power consumption by up to 80 percent when compared with FPGAs.

    Low-power consumption makes Nextreme-2 well-suited for applications that demand power efficiency to help reduce system cost and meet stringent power budgets.

    The Nextreme-2 Family also includes up to 56 multi-Gigabit IOs (MGIOs) each capable of operating at 6.5Gbit/s providing 364Gbit/s bandwidth. The inclusion of the MGIOs makes Nextreme-2 a compelling alternative to FPGAs and ASICs for high performance networking applications such as switches, routers, traffic management, metro transmission and mobile backhaul. Nextreme-2 delivers ASIC performance with rapid turnaround time and low upfront cost.

    Free Diamond Standard access
    eASIC also provides free access to the Diamond Standard microprocessor and DSP cores from Tensilica. This enables embedded system designers to develop Diamond processor-based SoCs for applications in any production volume.

    Tensilica's processors range from a very small, low-power 32bit controller up to the industry's highest performance DSP core and a multifunction audio processor that has been designed into millions of cellular phones. The Diamond Standard family includes:

  • 106Micromdash;the industry's smallest cachless, 32bit RISC controller core
  • 108Minimdash;small cachless 32bit RISC controller with built-in DSP capabilities
  • 212GPmdash;a flexible mid-range 32-bit RISC controller
  • 232Lmdash;a mid-range 32bit CPU with Memory Management Unit for Linux OS support
  • 570Tmdash;a high-end 32bit CPU core
  • 545CKmdash;a high performance DSP core
  • 330HiFimdash;a low-power, 24bit audio DSP processor supported with popular audio and speech codecs

    - Clive Maxfield
    Programmable Logic DesignLine

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