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DDR regulator fits low-power memory termination

Posted: 08 Aug 2008 ?? ?Print Version ?Bookmark and Share

Keywords:memory? DDR? memory interface? regulator?

Texas Instruments Inc. has launched a sink/source DDR termination regulator that is suited for all power management requirements for DDR, DDR2, DDR3 and DDR4 low-power memory termination. The simplified regulator requires only 20?F of ceramic output capacitance, almost 80 percent less capacitance than other solutions. The device promises to have smaller and lower-cost DDR memory termination in modern, high-memory content electronics like digital TVs, STBs, VGA cards, telecom, datacom, notebook and desktop computers, along with other consumer electronics.

The regulator's wide-bandwidth internal transconductance, having Gm amplifier and integral dynamic voltage positioning offers ultrafast transient response with minimal external output capacitance. In a typical application with a -1.5A to +1.5A load step, the output voltage variation is less than 25mV.

TPS51200 is designed to work with bias voltage between 2.375V and 3.5V, which makes it very appealing in many systems where only 2.5V or 3.3V rail is provided. The device also has the S3 sleep-state control during suspend to RAM.

It can also be employed as a general-purpose, high-performance low dropout regulator with an input range from 1.1V to 3.5V. The device has tracking start-up and shutdown features when the enable pin is connected to the system bus voltage, which makes the design process simple by helping the designer to easily implement sequencing in multirail systems.

It enhances TI's broad portfolio of DDR memory power solutions such as TPS51100 DDR termination regulator, TPS51116 DDR Power Switcher with integrated sink/source LDO and TPS40042 low-voltage tracking switching regulator for DDR termination. The TPS51200 also fits TI's DDR, DDR2 and DDR3 PLLs and LDOs for memory technologies such as SN74SSQE32882, PLL integrated DDR3 register for registered DIMMs.

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