World's first 3D chip technology surfaces

BeSang fabricated demonstration chips with 128 million vertical transistors for memory bit cells above their control logic. The ICs were designed at the National Nanofab Center and Stanford Nanofab. BeSang said its process protected by over 25 patent applications will allow flash, DRAM and SRAM to be placed atop logic, microprocessor cores and SoCs.

BeSang claimed it achieved 3D by fabricating logic circuitry using a high-temperature process on the bottom and by fabricating memory circuitry using a low-temperature process on top of the logic. By placing logic and memory on different layers of the same 3D chip, the company's process packs in more die per wafer, which leads to lower costs per die.

Humble beginnings
"BeSang was founded five years ago to develop 3D IC technology," said Sang-Yun Lee, founder and CEO, BeSang. The company has released a single-chip 3D IC process that is ready for commercialization. "By using a low-temperature process and orienting vertical memory devices on top of logic devices, we make more dies per wafer. This is how the cost per die goes down," he added.

At BeSang (translated as 'flying high' in Korean), Lee perfected the first true 3D IC process with former Samsung engineer Junil Park, who developed the first atomic layer deposition tool for high-k dielectrics. Because the new IC processing technique does not stack dies, the company said normal cooling techniques will work since no additional heat is generated by its slightly thicker 3D chips.

Current planar (2D) chips that contain memory must surround their memory arrays with logic circuitry to address bits and perform logic functions. Placing memory and logic along each other pushes the use of long interconnection lines between the two.

BeSang has placed logic circuitry on the bottom layer and the memory bit cells on the higher layers of the 3D chip, enabling very compact designs with very short interconnection lines between them.

Formation of 3D ICs
"Before BeSang's design came, all other past attempts were pseudo 3D," said Simon Sze, who co-invented the floating-gate transistor for non-volatile memory cells in 1967 at Bell Labs. Sze is now a professor at the National Chiao Tung University in Taiwan. "SoC put logic alongside memory on the same chip, but have had to compromise on performance since both were fabricated with the same process. By putting the memory devices on top of the logic devices, using separately optimized processes, BeSang is increasing density without compromising performance."

BeSang's process works by first fabricating the logic on one wafer with normal vias and interconnection layers. Then memory devices are fabricated separately on a donor wafer, and the two wafers are aligned and bonded to form a single 3D unit.

Because logic and memory are processed on different wafers, both can use normal 850°C processes that have been separately optimized. The two wafers are then sent to another line, where they are precisely aligned and bonded using a proprietary low-temperature, 400°C process.

The donor wafer essentially contains one vertically oriented bit cell, which, after bonding, is etched into millions of pillar-shaped transistors that control individual bit cells. The final step interconnects the individual bit cells and caps the 3D wafer with final metallization layers.

Cheaper cost
"The cost of BeSang's 3D chips should be cheaper because you reduced the overall chip area by putting all your logic in one process on the bottom wafer, putting all of your memory, using a different process, on the top wafer, and using the conventional vias to interconnect them," Sze predicted.

Demonstration chips were processed on 8-inch wafers using 180nm CMOS technologies. The test chip contains 128 million vertical transistors suitable for fabricating flash, DRAM or SRAM memory cells atop logic circuits. The bottom layer of logic was separated from the upper memory layer by single-crystal silicon, and two metal interconnection layers containing the vias between logic and memory. The top memory layer was lifted from the memory donor wafer, which contained alternating layers of n-type and p-type semiconductors. The donor wafer was reused four times, each time allowing one big vertical n-p-n transistor to be deposited atop the logic wafer.

After etching individual vertical transistors for bit cells, an additional metal interconnection layer capped the 3D wafer before dicing.

- R. Colin Johnson
EE Times