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DDR IP solutions speed up SoC design operation

Posted: 18 Aug 2008 ?? ?Print Version ?Bookmark and Share

Keywords:DRAM? memory? SoC design? IP solution?

Synopsys Inc. has introduced a full range of silicon- proven DesignWare DDR IP solutions for SoCs that need an interface to high-performance DDR3, DDR2 and DDR memory subsystems.

The IP solutions provide memory system capacity reaching 1600Mbit/s, the maximum data-rate of the JEDEC DDR3 specification. These include configurable protocol and memory controllers, integrated mixed-signal PHYs, including I/Os and verification IP. The DesignWare DDR IP portfolio offers designers with scalable solutions in reducing risk and hastening time-to-market for applications used in digital home, digital office, data center and storage.

The comprehensive IP portfolio consists of three product lines such as DDR3/2, DDR2/3-Lite and DDR2/DDR, all have been validated and fully integrated in Synopsys' silicon test chips and have two generations of DDR SDRAM.

Ease in connection
The DDR3/2 IP responds to the needs of the highest performance interfaces working up to 1600Mbit/s and has a wealth of in-system calibration capacities to simplify management of the interface at higher data rates.

The DDR2/3-Lite IP is an area- and feature-optimized IP solution working up to 1066Mbit/s with DDR2 or DDR3 SDRAMs. The DDR2/3-Lite IP is suited for SoCs that initially target DDR2 SDRAMs, and can be migrated to DDR3 when it has become more cost effective without the necessity to change the current SoC design.

The DDR2/DDR IP works at speeds up to 1066Mbit/s and uses leading 130-, 90- and 65nm process technologies.

The IP provides designers with the flexibility to work closely with DRAM components or DIMMs like support for write/read leveling as required with DDR3 DIMMs. To further enhance a memory interface applicable to each SoC, the DesignWare DDR IP allows customization of DRAM interface width, number of DRAM ranks, power I/O to signal I/O ratios and flexible I/O placement as required by the SoC package.

Each of the three IP product lines has a complete solution like configurable memory and protocol controllers, integrated PHY and verification IP. Unlike other DDR controller solutions, Synopsys gives designers a choice of two digital controllers. The DesignWare DDR memory controllers support up to 32 on-chip application buses, QoS-based arbitration and optimized memory transaction scheduling. The DesignWare DDR protocol controllers generate efficient DDR control and protocol translation giving the customers the chance to implement their own enhanced custom memory scheduler.

Meeting expectations
Complementing the digital controllers are the integrated, hardened PHYs, including the application specific I/Os, DLLs, PLLs and other PHY logic, simplifying timing closure in the SoC design flow and within the timing budget for the total DRAM interface.

"All generations of DDR interfaces remain a top priority for customers designing complex SoCs," said Desi Rhoden, executive VP of Montage Technology and chairman of the JEDEC JC-42 Memory Committee. "As part of the DRAM standards committee, Synopsys anticipates future DRAM products and aims to develop memory interfaces to match DRAM availability timelines and targets," he added.

"Meeting timing closure at the latest DDR speeds is very challenging," said John Koeter, senior director of marketing, IP and services, Synopsys. "Synopsys' leadership in analog and digital IP designs helps us to deliver a wide range of silicon-proven DDR IP that meets the unique needs of each end application and aids to reach timing closure at faster data rates with less risk," he stressed.

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