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Group boosts viability of PCIe standard

Posted: 20 Aug 2008 ?? ?Print Version ?Bookmark and Share

Keywords:PCIe? switch? interface? protocol? memory?

The HyperTransport Consortium speeds up to boost both its chip-to-chip interconnect as well as a board-to-board version that has yet to gain market traction. This is in relation to PCI Special Interest Group (PCI-SIG)'s next big leap in defining the PCIe 3.0 standard. The group has given details about an update of its current PCIe 2.0 standard that will be out early next year. Chipmakers start to roll out second-generation parts for Express 2.0, including a set of switches with built in direct memory access announced by PLX Technology.

Advanced Micro Devices Inc. heads developing for HyperTransport that will primarily be used as an integrated chip interconnect on its processors. PCIe has a wider scope because it is used in both Intel Corp. and AMD PCs and is gaining popularity in embedded markets.

HyperTransport ver 3.1, announced recently, can carry up to 6.4GT/s at rates up to 3.2GHz, up from 2.6GHz. It offers maximum theoretical throughput of 25.6GBps on a 16bit link, about a 23 percent increase over the 3.0 ver released in 2006.

By contrast, the existing Express 2.0 spec runs at up to 5GT/s and can deliver 16GBps aggregate on a 16-channel link. The 3.0 ver, set for release in late 2009, will handle up to 8GT/s and deliver up to 32GBps.

Mum on next projects
The HyperTransport group is not commenting on any work of its next major revision beyond the ver 3.1 midlife kicker. It is still looking closely on the latency of ver 3.1, typically a strong point for the technology.

"Overall, ver 3.1 has no dramatic impact in performance, but that is in response to the market that asked for a balanced design with more performance and manageable power consumption," said Mario Cavalli, general manager, HyperTransport Consortium.

The interconnect uses new scrambling, training and retry mechanisms as well as enhanced cyclic redundancy checking. "We have eaten into some of the margin in our electrical specs to maintain trace length, and there will be a slight increase in power use that the group has not yet not characterized," said Jeff Underhill, a HyperTransport member from AMD.

Separately, the group has revised its Higher Technical Examination Programme (HTX) specification for board-to-board links to the ver 3.0 data rates. "We didn't want to push the connectors to a full 3.1 speed because we wanted to avoid the capacitance it would create on the traces," said Underhill.

The faster spec aims to enable FPGA-based coprocessor boards. "Our recently released Stratix IV family of FPGAs was designed from the start to support HT 3.0 and will enable strong performance for HTX3 board designs," said Misha Burich, senior VP of research and development at Altera Corp, in a press statement.

Presently, only four boards of any kind have been using the HTX link released in late 2004 and two of them are no longer in the market, said Cavalli.

"As a niche within a niche, HTX is not going to have volumes or breadth of mainstream boards to rival PCIe," said Jag Bolaria, senior analyst, The Linley Group. "With increasing performance and features for Express as well as its momentum, it's challenging for HTX to maintain a long-term sustainable position," he added.

Partnered with AMD servers
Other analysts noted that as much as 98 percent of the use for the HyperTransport chip interconnect is tied to AMD server CPUs. "I have seen very little use of HyperTransport beyond that application, except for some Cisco Systems ASICs a few years ago," said Steve Berry, president, Electronic Trend Publications.

Meanwhile, the PCI-SIG has identified a number of protocol extensions and electrical enhancements, some of them for the coming Express ver 3.0 that it will roll into an update of the existing ver 2.0 by early 2009. Some of the features were initially discussed as part of an ad hoc Geneseo group led by Intel.

Revised features
First among the enhancements is support for atomic operations, a semaphore-based memory locking approach to enable coprocessor boards to link directly to computer CPUs. Other updates for ver 2.1 include a handful of enhancements to bolster performance and lower latency and power use.

The group faces plenty of work getting to the 8GT/s capabilities of the planned Express ver 3.0. "The electrical validation is our primary challenge, the long pole in the tent," said Al Yanes, chairman of the PCI SIG.

The group does not expect to know until the middle of 2009 whether ver 3.0 will be able to be fully backward compatible with the first generation of Express which runs at up to 2.5GT/s. Members are also still exploring whether the new spec will be able to support the full 20-inch trace lengths and two connectors used for some server blade daughter cards.

"Some companies are trying to define these elements in the labs before we release a spec," said Yanes.

"At these speeds, you really need lab validation not just paper analysis and simulation," he said. "We've done this kind of work before, but as you go to faster speeds you need to do more of it," he added.

"The type of equalization needed for the 3.0 data rates has not yet been determined. The group hopes to complete a ver 0.5 draft of the specification in a couple months," he noted.

New batch rolls
Meanwhile, companies start to roll out the second generation of their chips for the Express 2.0 standard. PLX has announced three new switches for the spec, its first to integrate DMA capabilities.

"We believe we are the first to offer DMA on a PCIe switch to the customers," said Krishna Mallampati, senior product marketing manager, PLX.

With integrated DMA, system designers can use processors that have no or limited DMA capabilities, saving cost and power. The chips target a wide range of servers, storage systems, network gear and embedded systems.

PLX shipped its first Express 2.0 chips last December and now offers 14 devices for the standard. "It has shipped three million Express parts to date. One hundred percent of our design efforts are now on Express 2.0," said Mallampati.

- Rick Merritt
EE Times





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