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Low-cost implementation of digital oscilloscope in Nextreme structured ASIC

Posted: 27 Aug 2008 ?? ?Print Version ?Bookmark and Share

Keywords:structured ASIC Nextreme? oscilloscope? digital? application note?

In the deep-submicron design era, it is clear that standard cell ASIC has become far too costly for most applications and its lengthening turnaround time is an additional drawback. The high upfront mask charges, together with costly EDA tools and large design teams required for completing a design, inhibit the access to the advantages of standard cell: lowest unit cost and highest performance. At the other end of the custom design spectrum, the FPGA solution often lacks the performance or power required, and although the upfront NRE it eliminated, the unit cost is the highest. To satisfy the electronic designer's project needs, structured ASICs are increasingly becoming the ideal choice for custom silicon applications.

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