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Winning the power challenge

Posted: 01 Sep 2008 ?? ?Print Version ?Bookmark and Share

Keywords:SoCs? DSPs? MCUs? system-level design?

Power!from the design perspective, less is more but too little is never enough. We live in a power-constrained world. Battery-powered systems may be the most talked about, but the power problem is everywhere!from kilowatt-rated industrial motors to mobile phones to sensor-activated devices that wake up once a week to send telemetry data. Energy consumption in the United States alone is forecast to increase by 32 percent by 2020. This appetite for power places a serious strain on natural resources, the grid, our wallets and business growth.

The march toward a more energy-efficient future will only make power efficiency more critical.

Engineers have been wrestling with the power problem for more than a decade, resulting in some significant strides in power management chips, systems and software.

At the fabrication level, process engineers have pushed down supply voltages and shrunk transistor sizes. DSP, applications processor and MCU designers are becoming particularly inventive with everything from a growing number of power-saving modes, to clock gating, to low-power cell libraries that complement low-power processes. System designers and software engineers have also developed a long list of options.

As product features grow and consumer expectations rise, the imperative to do more with less never changes. Semiconductor technology is playing a key role in energy conservation by combining efficiency and intelligence. Building efficiency into the chips and system designs that go into products we use daily helps take some of the responsibility from the consumer. So how do we get to the next level? One way for the industry to plot a course is to examine trends and see where they lead. Integrating the techniques and technologies will probably supply at least part of the answer. It may well be!as with many things in life!the whole is greater (or in this case, less) than the sum of the parts.

Nuanced process technology
The migration from 90nm to 65nm to 45nm process nodes has produced lower power chips in large part because higher density chips run at lower voltages!and power scales as a square of voltage. There are tradeoffs, however, because the thinner isolation layers of advanced processes allow greater leakage current when a particular circuit is quiescent.

To control power loss from active currents during the periods when a DSP, applications processor or SoC is not adding functional value, IC designers have invented techniques such as clock gating, which turns off selected parts of the chip when they are not being used. More dramatic results can be achieved by turning the entire chip off when it is not being used by the system. While effective, this technique sometimes calls for the intervention of an extremely low-power MCU. This also requires very tight MCU-SoC linkage because when the system calls for the larger chip to be turned on, it must happen instantaneously and the SoC must also wake up quickly.

Although these techniques continue to be very valuable, more nuanced approaches can add to power savings. Texas Instruments' Smart Reflex technology, for example, takes advantage of variations over process corners and monitors a device's activity, operating mode and temperatures at silicon junctions. This data allows system designers to optimize power efficiency by dynamically adjusting voltage and frequency. Smart Reflex technology can also coordinate power usage in multicore chips to cut down on chip-level power.

Inter-chip coordination
While many power advances have been realized by DSPs and SoCs, they are, by definition, large gate-count devices. Depending on duty cycle, it sometimes can be more power-efficient to move some functions off-chip, for example, by using a low-power MCU as a system supervisor. But two requirements must be met: inter-chip communication must be fast, reliable and efficient; and the MCU must operate at extremely low power and offer fast wake-up and shutdown times.

Figure 1 illustrates a small MCU power-sequencing and power managing a main processor. A software routine on the MCU enables the main processor regulators in the proper order and uses its internal ADC to verify when the supply rail has reached the proper voltage. When the main processor is not needed, it can be turned off using the shut-down feature of the regulators and saving the 70? to several milliamps consumed by the main processor.

Figure 1: MCU power-sequencing and power managing a main processor.

Systems that require simple, always-on functions are frequently more power-efficient if these tasks are performed by a companion MCU instead of a high-gate count SoC or DSP. Other such system or supervisory functions include:

?Power supply monitoring and reset

?Power supply sequencing

?Real-time clock keeping

?Human interface management

?Battery management

?Display management

DSPs typically have multiple power rails that must be sequenced at power-up for proper operation. At the system level, power supply monitoring, reset supervision and power supply sequencing are all basic supervisory functions that are!more often than not!handled by a fixed-function device. System designers should consider four key features when selecting a DSP for their low power design:

    ?Look for large on-chip memory.

    ?Select a DSP with a high degree of control over peripherals, as this translates directly into additional power savings.

    ?Choose a DSP that offers multiple standby states.

    ?Select a DSP that offers development software specifically designed to optimize power utilization and minimize power consumption.

    Useful as they are at managing power for the processors, these fixed-function devices cannot do anything else for the system, and specifically cannot turn off the main processor when it is not needed. Replacing the device with a small, low-power MCU provides the added capability to power-manage the main processor, while implementing the sequencing, monitoring and system level supervision functions.

    Returning to the second requirement!that the MCU itself be a power miser!raises questions that the system designer must consider when selecting an MCU as the supervisor processor. Process technology and operating voltage are, of course, critical. But MCU architecture can be equally important. In many ways, the same power optimization rules apply for MCUs as SoCs or DSPs.

    MCUs should, for example, offer:

    ?Sufficient on-chip memory to significantly reduce or completely eliminate off-chip data access

    ?Integrated analog blocks that are not accompanied by an analog performance hit

    ?The ability to turn their own peripherals on and off

    ?DMA capability when data is only being moved back and forth.

    DMA capability is particularly important because a significant amount of energy can be wasted when the MCU is merely collecting ADC samples or moving data. DMA makes it possible for an ADC to store data samples directly into memory, allowing the MCU to go into standby until the required number of samples is taken. Then the MCU wakes up to process the samples, and returns to standby as quickly as possible.

    One recent innovation in low power for MCUs, such as TI's new MSP430F5xx MCU generation, is the ability to adjust core voltages and clock speed dynamically according to the processing load. As mentioned, MCU power is proportional to the voltage squared and maximum MCU clock speed is proportional to the core voltage. During times of high or low processing loads, the user can optimize the MCU power by scaling the clock speed and core voltage on the fly.

    The interaction between SoCs, DSPs and their power supplies is a critical system-level issue for both power consumption and system performance. Too large a supply wastes energy; and, when the supply is too small, performance suffers. Sizing the power supply to perfectly match the needs of the larger IC's requires detailed knowledge of the DSP's maximum load at maximum voltage. However, that information is usually not available until very late in the DSP's design cycle.

    Power-up and power-down sequences also require precise coordination. Because SoCs and DSPs typically have multiple power rails that must be powered in a specific sequence, the power supply must be capable of responding to a status change within the time demanded by the larger chip. Multiple attempts waste both power and degrade performance.

    Power management ICs and related components continue to become more efficient through process technology improvements and reduced power operating modes that allow for lower losses in the power management IC itself. For example, process technology improvements allow for lower power switch resistances, lower gate capacitances and lower leakage currents to reduce I2R losses, switching losses and biasing/quiescent currents, respectively. These types of advancements were used, for example, to reduce power consumption in TI's newest low power DSPs and applications processors, which use one-third the power of previous devices.

    Moreover, most new power ICs have a Power Save Mode that only turns on the pulse width modulator (PWM) switch when the output voltage begins to drop, thereby reducing switching losses instead of continuously switching, as shown in the efficiency curves below with the TPS62290, 1A step-down converter in 2mmx2mm QFN.

    Figure 2: Efficiency power save mode and forced PMW Mode vs output current.

    Playing nice together
    As power efficiency technology moves into a new generation, it has become more sophisticated!depending more and more on the interaction between ICs. This trend raises two questions: Is the support chip really capable of communicating with the DSP or SoC to the greatest possible degree? Will inter-chip communication degrade system performance?

    From the trends we've seen so far, it appears that the next generation of power efficiency technology will require a heavy dose of institutional knowledge integration. As a holistic, system-level view of power management!in addition to ever-advancing chip technologies!becomes increasingly important, open conversations and collaboration between DSP, SoC, MCU and analog power management designers are critical.

    Additionally, semiconductor companies must find ways for system designers to take advantage of the sophisticated techniques built into the chips. Otherwise, all of the potential energy savings cannot be wrung out of a system.

    Providing system designers with tools that allow them to turn the power management knobs built into ICs to optimize their system is an important step in achieving the next generation of power efficiency. From a system-design perspective, this also requires that components work together at a very high level of sophistication, and this begins while the SoC or DSP is still being designed. Analog, MCU and power supply designers can provide invaluable input to the SoC or DSP design team.

    About the Authors
    Leon Adams
    is the DSP strategic marketing manager for TI. Kevin Belnap is the product marketing manager for TI's MSP430 ultralow power MCU group. Jeff Falin is a factory applications engineer with the high performance analog, portable power applications group at TI.

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