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3D-TSVs spark packaging revolution

Posted: 01 Sep 2008 ?? ?Print Version ?Bookmark and Share

Keywords:3D-TSV wafers? 3D integration with through-silicon vias?

By 2013, 59 percent of 3D-TSV-packaged chips will come in stacks. (Click to view full image)

Chips face the so-called "More-than-Moore" 3D integration route in order to pursue the continued aggressive scaling demanded by the historical law.

The whole industry supply chain is involved, from IDMs to fabless companies and CMOS foundries, outsourced semiconductor assembly and test entities to substrate and circuit assembly players as well. 3D integration with through-silicon vias (3D-TSV) will accelerate the consolidation happening in CMOS wafer fabs and the shift toward the fabless foundry model.

3D-TSV wafers will ship in the millions and will have the potential to impact as much as 25 percent of the memory business by 2015, according to market research company Yole Developpement. Excluding memories, 3D-TSV wafers could account for more than 6 percent of the total semiconductor industry by 2015.

Push for 3D
Motivations for going to 3D include achieving smaller form factor with increased package densities to meet bandwidth, RF and power consumption performance improvements, and to reduce cost. Reliability is another motivation, as higher reliability systems can be manufactured through the vertical integration of several layers using 3D-TSVs instead of wire-bonds or flip-chip interconnects and using 3D stacked wafer level optics instead of plastic injection molded lens modules. In addition, 3D is an enabling driver for the introduction of new systems into harsh and space-constrained application environments such as in automotive, telecom and consumer markets.

First used for image sensors, 3D packaging tech will enter into, and grow in, various semiconductor segments.

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