Developing system-level validation routines

During the system design and validation process, designers may require stress testing of their platforms and in system testing of flash memory. Some test routines may inadvertently expose the systems flash memory components to stress far exceeding operational stress and result in incorrect analyses of system reliability. To better engineer system level test routines and to validate the flash memory subsystem, Spansion offers several guidelines in this application note.

View the PDF document for more information.