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Accelerating MPEG-4 video decoding with an Xtensa processor

Posted: 04 Sep 2008 ?? ?Print Version ?Bookmark and Share

Keywords:MPEG-4? processor Xtensa? video?

This application note shows how high-performance implementations can be made for the Inverse Discrete Cosine Transform, variable length decoding and motion compensation using instructions developed in TIE. These optimizations are combined to show that the MoMuSys MPEG-4 reference code can be optimized by a factor of 50. The original code required a processor speed of at least 400MHz while the optimized code only required 9MHz without writing any assembly code.

View the PDF document for more information.





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