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Valuing substrate parasitics in RFIC designs

Posted: 16 Sep 2008 ?? ?Print Version ?Bookmark and Share

Keywords:RFID? digital circuit? routing? noise? parasitics?

Often, there is a need to simulate RFIC designs with substrate parasitics to accurately represent high-frequency effects in actual silicon. Generally, parasitics appear from a chip's surface layers, especially from metallization routing and coupling, or from the resistance and capacitance (RC) parasitics of the silicon substrate. Substrate parasitics are especially troublesome when calculating the effects of substrate noise injection and subtle interactions of high frequency ground loops.

For sensitive circuits, such as a voltage-controlled oscillator (VCO) in a PLL, it is important to consider the possibility of substrate parasitic coupling. Nearby digital circuits can inject current into the substrate. However, before substrate parasitics can be simulated in a particular IC process, it is necessary to create a technology extraction file and correlate it to silicon. Once the extraction process is validated, substrate parasitic extraction can become a helpful step in RFIC design.

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