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1.5GHz FPGAs target ASIC sockets in complex systems

Posted: 18 Sep 2008 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? circuitry? ASIC? memory controller?

Achronix Semiconductor Corp. uses asynchronous circuitry to deliver a 1.5GHz FPGA samples. The startup hopes to use its three-fold lead in data rates to grab ASIC sockets in high-end communications, test and other systems beyond the reach of existing parts from Altera Corp., Xilinx Inc. and others.

Achronix's success in delivering its latest technology remains to be seen. It has lined up a suite of tools and silicon intellectual property that will be widely produced in 1H 09.

The new 65nm device represents its second attempt in producing a commercial product. About a year ago, the company killed its so-called Ultra chip, a 90nm, 1.93GHz version announced in 2006, saying it lacked the merits that users are looking for.

"Assuming they can deliver, they would be filling a void that's existed for quite awhile, providing a new top end for the FPGA market," said Rich Wawrzyniak, analyst, Semico Research. "There's a wide gap between the top end of ASICs and FPGAs," he added.

"It's certainly a viable approach to take," said David Greenfield, senior director of product marketing for high-end FPGAs, Altera, speaking of a move to faster data rates. "We have looked at it before and will continue to look at it," he added.

Altera's move
Altera decided to build more dense products rather than faster ones with its 40nm chipset to ship later this year. The new Stratix parts will have the same native speeds of about 350MHz of its existing 65nm chips, but the new chips will double to as many as 700,000 the number of logic elements. They will support hard cores running at up to 550MHz.

"There are multiple ways to address performance in the critical path for any particular design, sometimes it's through the clock and sometimes it's elsewhere," said Greenfield. Only about 10 percent of customers for Altera's Hard Copy FPGA-to-ASIC service are seeking its 30 to 50 percent higher data rates, he added.

The Achronix SPD60 is built up from relatively conventional four-input look up tables (LUTs) encapsulated in a 1.5GHz synchronous logic. Inside that frame the chip employs routing elements made up from basic transmit and receive components that use asynchronous acknowledgments rather than clock cycles to stage the flow of data.

The approach allows higher throughput than traditional flip-flops that gate logic elements in traditional FPGAs. It emerged from research in asynchronous logic by two company founders such as Rajit Manohar, associate professor at the School of Electrical and Computer Engineering at Cornell University and Clint Kelly, one of his doctoral students.

The company is one of a growing group of startups, including 10Gbit switch designer Fulcrum Microsystems, which taps asynchronous logic to leapfrog traditional devices.

"Other FPGAs have to deal with a big global clock that needs to be distributed, skewed and balanced that fundamentally limits performance," said John Lofton Holt, CEO and cofounder, Achronix.

Target positioning
The startup envisions a family of four Speedster chips all running at up to 1.5GHz and supporting up to four 1,066MHz DDR3 memory controllers. The initial SPD60 includes 47,000 LUTs and can hold up to 20 10.3Gbit Serdes licensed from the former Snowbush Microelectronics.

Achronix plans to follow up the part with a high end SPD180 with 163,000 LUTs and room for twice as many 10G Serdes. A low-end part will have two memory controllers, 24,000 LUTs and suitable for a 31mm x 31mm package. The devices range widely in price and power use from $200 and less than 20W to $2,500 and more than 40W.

Holt claimed the family can address a $1.7-billion slice of the ASIC market that traditional FPGAs cannot reach. "We can become a billion-dollar company without winning a single existing Xilinx or Altera socket," he said.

Lacking essentials
In 2006, Achronix had released its 1.93GHz Ultra chip built in a 90nm process at Chartered Semiconductor. But the startup has found it lacked features that prospective users want and consumed more power than expected.

The Ultra had about half the density of the current product samples and significantly higher power use. It also lacked support for 10G Serdes which was only available at the time in a block from Snowbush Microelectronics designed for a 65nm Taiwan Semiconductor Manufacturing Co. Ltd process.

"Not having a 10G Serdes could have excluded us from communications systems, a third of our potential market," said Holt. The 65nm TSMC process also could accommodate a broader product family, he added.

Engineers are hammering out standards for 40Gbit/s and 100Gbit/s Ethernet systems that carriers are eager to deploy in their core networks. While that work is not yet complete, many believe 10G Serdes will be essential to support the specifications.

"We think demand for 10G serdes will kick in early next year," said Greenfield. "Verizon Wireless, AT&T and others want to deploy these 40Gbit and 100Gbit systems as early as 2010, so they need to do field trials in late 2009 and so chips in the labs are expected in early 2009," he added.

"Altera has running in its labs internally designed for 10G Serdes that will be available for its FPGAs early next year," he noted. Its 40nm FPGAs will initially ship late this year with its 8.5G Serdes.

Innovative components
Many new chip architectures are employed to achieve desired performance at the cost of requiring radically new programming tools. Earlier, Holt insisted that the Achronix parts should resemble traditional FPGAs so they could use existing tools as much as possible.

Thanks to its synchronous frame and use of traditionally organized LUTs, Achronix was able to get support in its versions of front-end tools, including Mentor Graphics' Precision and Synplify Pro from Synopsys Inc.

"A number of other FPGA startups would not even be able to get support from a Mentor Graphics or Synopsys," said Holt. "Some of these guys even require schematic entry or by-hand design."

In January, Achronix shipped its own back-end tool that handles place and route, timing and critical path analysis. It aims to support a look roughly similar to tools from Altera and Xilinx.

"At the board level, other chips don't have to know anything about our oddball architecture," said W. Denny Scharf, strategic marketing manager, Achronix. "People can implement a design without even realizing this is asynchronous," he added.

As for silicon IP, the startup claims it has a long list of partners whose blocks can be readily implemented on the chip. It includes a wide range of interface blocks including Gbit and 10Gbit Ethernet, 2.5GHz and 5GHz PCIe, Infiniband and Fibre Channel. The company has also licensed a 32bit processor core from Cortus SA.

Achronix took in $34.4 million in venture funding in a Series A Round in 2007. Earlier, it was self-funded.

- Rick Merritt
EE Times

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