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IBM opens gates of 300mm fab

Posted: 25 Sep 2008 ?? ?Print Version ?Bookmark and Share

Keywords:IBM 300mm fab? 45nm node? processor?

Up until recently, IBM Corp. refused to reveal any information about its semiconductor operations, keeping it a closely guarded secret. But in a recent presentation and fab tour, IBM's Microelectronics Group opened the kimono and disclosed the inner workings of its most advanced 300mm fab, which is called Building 323.

During the presentation, IBM revealed that it will not deploy high-k dielectric materials for logic chip production until the 32nm node. It was widely believed that IBM and its partners, namely Advanced Micro Devices Inc., could bring out high-k as early as the 45nm node.

In another development, IBM is quietly building out the first phase in the new annex of the 300mm fab. The new and previously-announced annex is producing ASICs and game chips based on 65- and 45nm design rules, with both 45- and 32nm technology in R&D. It's no secret that IBM makes the processors for video console giants Microsoft, Nintendo and Sony.

IBM has sealed off the second phase of the new extension and declined to say when it will move into operation. The second phase of the new annex will produce 32nm designs, with 22nm technology in R&D, said Michael MacDonald, 300mm manufacturing manager for IBM's systems and technology group.

IBM's 323 fab has a total capacity of 500 to 600 wafers per day. The IBM fab is using 193nm immersion scanners from ASML Holding NV and wafer-track systems from Tokyo Electron Ltd (TEL).

In the new annex, IBM has a total of five of ASML's 1900i line of 193nm immersion tools. According to IBM, ASML's 248- and 193nm scanners are handling both the critical and non-critical layers in the fab.

Applied, FEI, KLA-Tencor, Muratec, Novellus, Veeco and others are among IBM's tool suppliers in the 323 fab. IBM is reportedly using TEL's reactors for the production of high-k materials. For low-k dielectrics, IBM for some time has developed its own films, dubbed Sicoh, denoting the silicon-carbon-oxygen-hydrogen mix in the material.. The films are processed in chemical vapor deposition reactors, reportedly those from Applied Materials Inc.

Building 323 progress
With much fanfare, IBM opened Building 323 in 2002. At that time, IBM's $2.5 billion fab represented the largest private-sector investment in New York state history and the nation's largest since 1995. The 300mm fab was part of a $5 billion capital investment program launched in 2000 to create a broad-based manufacturing hub in the state.

IBM basically refurbished the plant. Until 1993, the fab had been used to manufacture bipolar chips on 5-inch wafers. To accommodate the 300mm equipment, IBM had to take down 4.5 million pounds of concrete to raise the roof 4 feet.

In its facility are three basic 300mm fab modules. The first module, which is a giant 140,000-square-foot facility, has been producing chips for some time.

The new annex has two modules. The first phase of the new annex is a 40,000-square-feet complex. The first phase is ramping up 65- and 45nm designs, with 45- and 32nm devices in R&D. Meanwhile, the second phase of the new annex is a 32,000-square-feet complex. The second phase, which is not in operation, is projected to ramp up 32nm designs, with 22nm devices in R&D.

At the time of its grand opening in 2002, IBM expected to produce 0.1? chips by 2003. The company claimed it would produce designs based on low-k dielectrics, copper interconnects and silicon-on-insulator (SOI) technologies.

Today, IBM is ramping up 45nm designs, with 32nm on the way. IBM develops ASICs and other chip products. It also provides foundry services and intellectual property for customers.

'Fab club'
IBM's fab is geared to develop products for the company's servers and other products. "Our primarily goal is to provide technology that goes into IBM products," said Subramanian Iyer, chief technologist for the Semiconductor Research and Development Center within IBM's systems and technology group.

Previously, like many chipmakers, the company was developing its processes on its own. But several years ago, the company formed an alliance to develop a common process, as a means to spread the risk and R&D dollars. Today, IBM's so-called "fab club" includes seven companies: AMD, Chartered Semiconductor, Freescale Semiconductor, Infineon Technologies, NEC, Samsung Electronics, STMicroelectronics and Toshiba.

Many of IBM's partners have already co-developed several generations of process technology. Process R&D is conducted with partners at IBM's R&D centers in Yorktown, New York and Almaden, California, as well as at Albany NanoTech in Albany, New York. On the foundry side of the equation, the processes are developed and transferred to three companies: IBM (Building 323), Chartered (Fab 7) and Samsung (Fab S1).

But unlike Intel Corp., IBM and its partners do not adhere to a strict "copy exact" program, in which the companies insert identical tool sets in their respective fabs. "Each company has the choice [to procure] their own equipment," said Mark Dougherty, 300mm engineering manager within IBM's system and technology group.

There is a slight change in direction on the procurement front, however. At present, the companies are beginning to collaborate more on fab-equipment procurement cycles, he added.

45nm and beyond
Needless to say, IBM and its partners continue to move full speed ahead on the process front. IBM, Chartered and Samsung are said to be processing chips based on a 45nm technology. This process includes the usual technology suspects: 193nm immersion (ASML); ultra-low k (IBM/Applied); copper interconnects and silicon germanium (SiGe).

Singapore's Chartered is reportedly also developing a half-node 40nm process, but Samsung has yet to make a decision about that technology. TSMC has recently rolled out a 40nm process, while UMC is reportedly working on it.

In March, IBM and its partners claimed they would deliver high-k dielectrics and metal gates for the 32nm node. The partners claimed the circuits had, on average, 35 percent better performance than 45nm technology circuits at the same operating voltage. The 32nm technology also consumed between 30-to-50 percent less power than 45nm, with respect to operating voltage.

The companies said the technology will be available to IBM and its alliance partners in the second half of 2009. The 32nm process will also use immersion lithography, ultra low-k, copper and other features.

Some thought IBM would have high-k technology at 45nm. Instead of rolling out the technology at 45nm, IBM decided to stick with silicon dioxide. "We had the option" for bringing out high-k at 45nm, Iyer said. "It was working."

IBM and its partners are also working on 22nm technology. IBM and its joint development partners recently claimed they have developed the first working SRAM cell implemented in a 22nm manufacturing process. The cell was built at Albany NanoTech's 300mm research facility in Albany.

The key enablers for the 22nm SRAM cell include band-edge high-k/metal gate stacks, transistors with less than 25nm gate lengths, thin spacers, novel co-implants, advanced activation energy techniques, thin silicide and damascene copper contacts.

Shift to 'computational scaling'
Amid probable delays with extreme ultraviolet lithography, IBM also plans to extend 193nm immersion and move towards what the company calls "computational scaling" technology for the 22nm node and perhaps beyond.

Current optical lithography is expected to hit the wall at the 32nm node. "Computational scaling" sometimes called computational lithography is said to overcome those limits and extend 193nm immersion.

A key to "computation scaling" is a partnership between IBM and Mentor, which plans to devise a new resolution enhancement technique (RET) to enable 22nm designs and perhaps beyond. This RET technology, know as source-mask optimization, will not eliminate dreaded and expensive 193nm immersionwith double-patterning techniques.

Source-mask optimization is said to optimize both mask layout and illumination simultaneously to maximize image contrast in a scanner. The technology is said to provide a means to minimize the use of double-patterning by employing customized sources within the scanner, along with optimized mask shapes.

There are other components to "computational scaling:" virtual silicon processing with TCAD; predictive process modeling; design-rule generation and corresponding models; design tooling; design enablement; complex illumination; variance control; and mask fabrication.

- Mark LaPedus
EE Times

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