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Andes facilitates Taiwan SoC design

Posted: 01 Oct 2008 ?? ?Print Version ?Bookmark and Share

Keywords:Taiwan IC design? mobile Internet device? consumer electronics? IIC-Taiwan?

Driven by strong market demand for portable products, the consumer electronics sector swerves to the Internet-capability route, as touted by Mobile Internet Devices (MID). This move highlights the importance of a high-performance and low-power solution to create opportunities in the market. However, to integrate the Internet functionality, other applications' performance must improve as well. Thus, having a high-performance CPU core is suggested for high-end portable devices.

Andes Technology Corp. focuses on the development of embedded microprocessor silicon IP. Established in 2005, Andes now has a workforce of over 90 members. The company is focusing on the development of its 32bit AndesCore, microprocessor IP and tool chains. It provides IP cores for Taiwan IC design houses.

Three CE factors
Andes targets performance, power consumption and cost, the three major factors for portable CE. It has released high-, middle- and low-end cores, the N12, N10 and N9, respectively. The company showcased its entire series of cores and solutions at the International IC-Taiwan Conference & Exhibition (IIC-Taiwan) 2008.

According to Andes, the N9 and N10 cores adopt five pipeline solutions, while the N12 core uses eight pipelines. As more pipelines mean larger size, a key factor in SoC design would be the balance between cost and performance.

To judge performance, Andes refers to the CPU core frequency and the amount of functions the CPU core structure supports. According to Charlie Su, chief technical officer and VP of R&D/technical marketing at Andes, the N12 core has been developed using 90nm. It has reached 600MHz with 0.25mW/MHz. "Moreover, we have the ability to develop a CPU core with a frequency over 600MHz, and we expect to develop a 1GHz CPU core by 2009 or 2010. Andes will also continue to meet the market trend toward 65nm CPU core development," Su shared.

Andes has released a CPU core adopting Taiwan Semiconductor Manufacturing Co. Ltd's 90nm process node. The company also has a chip that adopts United Microelectronics Corp.'s 90nm manufacturing process. Andes projects 65nm product implementation in 2H 09 and move up to 45nm in the foreseeable future. Andes' CPU cores feature various functions for different configurations. If one core has 10 functionalities, customers have the option to choose what they want to use. Customers can also customize CPU cores for SoC differentiation.

Dealing with power issues
To address power consumption, Andes offers the AndesCool low-power solution. According to Su, portable products require low-power performance for long operating time. This demands improvement not only of the CPU core, but also of system and software technologies. Su said that Andes has been developing technologies outside the CPU core. "Thus, we can offer a reference flow for our customers, who can now take advantage of AndesCool to produce efficient SoCs," the executive added.

Ming-Hau Lee, director of IP service and marketing at Andes, added: "There are two segments for AndesCool. One, we add on several low-power technologies during CPU core implementation, and two, we adopt power management technology such as dynamic voltage and frequency scaling. This technology will be used for our CPU core. We have also been developing dual-core technology along with some software for products like MIDs. We expect to release the entire dual-core solution with OS or software in 2H 09."

"Adopting RISC and implementing low-power technology are the main means for us to offer different products. Our power management and low-power technology are designed for SoCs. We have the technology to help our customers produce SoCs with 1W-2W power consumption, or even lower," Lee noted further.

As cost is among the key factors to produce competitive CE products, Andes uses its 16/32bit mixable instruction set. This is used for creating smaller code size, thus saving memory space and achieving low cost targets. According to Lee, "When you design a 32bit CPU core, the straightforward thinking is to use a 32bit instruction set. However, via Andes' 16/32bit mixable instruction set, you can design some commonly used instruction with 16bit. Therefore, the 32bit space can be filled with two 16bit instruction sets. This is quite a good design for cost savings."

At present, Andes' high-end cores can support Linux. The middle-range cores are for Linux and some simple RTOS, while the low-end cores can support RTOS or SoCs that don't need an OS. "Now, we can support several RTOS like uCOS2. And because OS is important to applications, we will support even more OS," said Su. "Regarding the market segment, we will still focus on Taiwan customers this year. On the other hand, we will try to expand our market to regions like China, Korea or Silicon Valley in the U.S. in the near future."

- EE Times-Taiwan





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