Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Manufacturing/Packaging

Stacked microprocessor system promises better performance

Posted: 01 Oct 2008 ?? ?Print Version ?Bookmark and Share

Keywords:stacked microprocessor? chip cooling? dissipation heat?

Advanced microprocessors do the heavy number-crunching in all sorts of electronics systems, but these chips are hampered by the amount of heat that they put out. The microprocessors are typically flip-chips and require a fairly efficient heat dissipation system. Very often this system consists of a large metal heat sink carefully bonded to the back-side of the silicon.

To go to the next higher level of speed and performance, it would be useful to stack microprocessors in order to shorten interconnect distances, but the metal heat sink makes stacking impossible, and would not be able to cool the resulting increase in power density. As the International Technology Roadmap for Semiconductors makes clear, heat dissipation requirements will only become more severe as feature sizes shrink.

By the year 2018, the 18nm technology node will have been reached. Heat removal requirements will range from 151W/cm2 for cost-performance applications to 198W/cm2 for high-performance applications. Having a good alternative to massive metal heat sinks becomes more and more imperative.

Researchers at Georgia Institute of Technology's GigaScale Integration Group have taken an approach to cooling chips that has resulted in what may be the most efficient heat dissipation that is possible for stacked microprocessors. Group members include Muhannad Bakir, Deepak Sekar and Calvin King. Their work is funded by the Interconnect Focus Center Research Program and the U.S. National Science Foundation.

The side-view diagram of two stacked microprocessors is shown.

Vias for cooling
The stacked microprocessor system has two key features. First, the microprocessors in the stack are connected by through-silicon electrical vias (TSEVs) connecting adjacent chips. Second, the stack is cooled by deionized water that is pumped through vertical through-silicon fluidic vias (TSFVs) that are etched through each chip, and through horizontal microchannels that are etched into the back-side of each chip.

Bakir explains that the group is using "wafer-level batch fabrication for the advancement of electrical and thermal interconnects by developing low-cost high-density CMOS-compatible electrical and fluidic 3D interconnect networks in a 3D stack." The goal is to create a 3D fluid cooling system that will be capable of removing 200W/cm2 of heat.

The wafers are thinned down to a thickness of 250?m to 300?m. In the electronics industry generally, there are applications that thin wafers down to 50?m or even less, but the greater thickness is needed here in order to accommodate the horizontal microchannels. Most of the wafer, Bakir explains, is simply mechanical support. "We take advantage of that available silicon and etch channels directly in that silicon. So the fluidic channels are just a few tens of microns away from where you have your devices. We really try to get the liquid as close to the active circuitry as possible."

First, a thin layer of silicon oxide is deposited on the front-side of the wafer to serve as an etch-stop layer. The TSEVs are patterned and etched from the back-side of the wafer. A 1?m layer of oxide is grown on the walls of the TSEVs, a titanium-copper seed layer is evaporated onto the front-side of the wafer, and the TSEVs are electroplated with copper.

After this, the TSFVs and the microchannel trenches are etched into the back-side of the wafer. These features do not require plating.

A sacrificial polymer is then spin-coated onto the back-side of the wafer and fills the microchannels. Next, the surface is polished. A second polymer layer is then applied, and heat is used to remove the sacrificial polymer filling the microchannels, which are now empty but capped by the second polymer.

The electrical vias and the fluidic vias are both etched from the back-side of the wafer. Copper is used to plate the electrical vias, although other material such as tungsten can also be used. The fluidic vias are left empty, but at each end of a fluidic via a circular socket is formed.

Chip assembly
After the completion of wafer-level fabrication, the wafers are diced and the chips are stacked by a flip-chip bonder that can place the chips with an accuracy of less than 2?m. During assembly, sockets at the ends of fluidic vias are connected by a short 60?m length of polymer micropipe. The electrical vias are attached to solder bumps on the net die. Adjacent die are now connected by both electrical and fluidic vias as shown in the figure.

There remains a good deal of empty space between the die, which can be filled by a polymer (much as flip-chips are underfilled), although this step does not seem to be necessary. To date, the group has created stacks of four chips each. The deionized water, which is very efficient at removing heat, flows in microchannels and fluidic vias that are as little as 30?m from the active circuitry that is the source of the heat.

The performance advantage of a stack of microprocessors connected by TSEVs and TSFVs depends on the great reduction in distances. If two microprocessors are stacked, they are separated only about 250?mthe length of a TSEVinstead of being separated by many centimeters, as they would be if they were individually surface-mounted.

Design implications
The performance can beand undoubtedly will beenhanced even more by careful planning of the layout of each chip. The highest speed will be obtained when circuit blocks that communicate with each other most frequently are located at opposite ends of the same TSEV.

As of mid-2008, no TSVs of any kind were in production, but IBM had announced that it would commence production of stacked microprocessors using TSEVs in 2H 08. The announcement estimated that the distance that information would travel would be reduced by a factor of 1,000 compared to standard layouts. Since the pitch of signal interconnects is greatly reduced, bandwidth density can be much higher.

Because such performance enhancement is possible, it will make sense to begin the design of stacked microprocessor assemblies at the chip level in order to maximize speed advantages. It would be difficult or impossible, for example, to attempt to stack microprocessors made by different manufacturers.

Even though the technology is still in the development stage, Bakir believes that wide-scale production involving TSEVs and TSFVs might occur in the not too distant future. "I think TSEV technology is fairly mature fabrication-wise," he says. "It's not ubiquitous in the consumer market or anywhere else now, but I think people have done a fair bit of work on it to know its reliability characteristics, though it will be a bit longer before we have complete understanding of cost and reliability."

The technology that Georgia Tech has developed will first be used in high-end applications such as supercomputers and servers; applications that are not severely restricted by cost and that require highest performance. These advanced cooling technologies can also reduce the power dissipation of the data center since they are more efficient at extracting heat. And while the technology adds to manufacturing costs, Bakir notes it may be justifiable in applications that are more cost-sensitive given the performance gains that can be achieved.

- Tom Adams is a writer, photographer, consultant and holder of one patent relating to the inspection of devices.

Article Comments - Stacked microprocessor system promis...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top