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Chip package options abound

Posted: 01 Oct 2008 ?? ?Print Version ?Bookmark and Share

Keywords:chip packaging? cavity package? stacked-die?

When creating a new IC, all of the initial focus is naturally on the design. When it comes to tape-out, then fabrication, multi-project wafer (MPW) services are growing in popularity as deep sub-micron technologies become the norm, and both mask and wafer fabrication costs soar. However, device packaging is often overlooked until the end of process. This may be the result of some fabs and MPW providers having relatively little to offer with respect to packaging, or it may be simply that you see it as the last thing you need to worry about. In fact, choosing the right package both during the creation of a chip, for the test phase of development, and for the final device can shorten time-to-market and create tangible benefits for customers. The number of package choices has never been greater and some MPW providers now recognize the importance of providing chip developers with optimized packages throughout the development of silicon devices. Most frequently, this is done through partnering with established packaging specialists. Here is a look at some of the available options and what they have to offer.

Being able to carry out focused ion beam analysis and probing during development is important, and open cavity packages are ideal for such tests. These tests speed up design work and ensure device integrity before moving on to volume production. However, these packages were usually large ceramic types. These are expensive, and high-speed SI cannot be evaluated accurately because package interconnects are not the same as those that will be used in the final package.

Open cavity packages
Recent developments have changed all of that and open-cavity packages are now available in several popular formats including QFN/MLP, QFP and SOIC/SSP. These pre-molded packages meet the latest Jedec outline and footprint standards. Their copper lead frames are gold-plated to military standards, so they are mechanically stable and have very similar electrical characteristics to fully encapsulated, moulded types that would be used in volume production. Typical package sizes are from 3mm x 3mm to 10mm x 10mm.

Chip-scale packages
Relatively low cost, small size, and high performance make chip-scale packaging (CSP) a popular choice. It provides protection for the die surface, minimizes stress between the PCB and the die, and facilitates changes in interconnect arrangements between the die and PCB. High-speed signal performance is particularly good because interconnects are kept very short. Rather than the conventional process of wafer fabrication, dicing and packaging, the creation of wafer level CSP involves packaging complete wafers and then dicing them, as shown in Figure 1.

Figure 1: Producing wafer scale packages moves silicon dicing to the end of the process.

Creating a CSP involves covering the wafer with a layer of passivation (polyimide) then etching vias down to the bond pads, which are traditionally located around the outside of each device, and filling the vias with conductive material. A copper re-tracing layer is then deposited that connects to the top of the vias and forms a matrix pattern across the whole chip. Solder bumpingcreating the balls that will contact the PCBis achieved by depositing a thick layer of passivation, etching vias into this at the desired connection points, then filling the vias with solder. The top layer of passivation is then removed and surface tension makes the columns of solder form into ball shapes. The final construction is shown in Figure 2a. Highest performance is achieved by keeping critical signals on the outside of the device so that they have the shortest connections to the die. CSP also offers very good thermal performanceheat is easily dissipated because there is no insulating packaging surrounding the die.

Where space in the X-Y plane is at a premium, a stacked-die approach can be used. Stacked-die packaging allows for very efficient use of motherboard real estate, reducing size and weight, as well as contributing to system cost reduction. Taking the MPW routes with stacked-die packaging can allow complex systems to be prototyped earlier than waiting for a single IC to be developed. Using stacked die can therefore be a good way to prove that a design meets the required specification, on the way to moving everything onto a single process. For example, flash memory, digital and analog elements of a design can be produced on different die but housed in the same package. The technology also enables the flexibility of combining custom chips with off-the-shelf devices to reduce systems cost. Die is tested before being put into the stacks to ensure that only known good die is used and that waste is minimized. Three different approaches can be taken to stacked die construction: same-die stacks, pyramid stacks and overhand cross stacks. These are illustrated in Figures 2b to 2d.

Where two die are used, the maximum package heights will typically be in the region of 1.4mm. It is also possible to stack three or more die in a single package where board space is the prime restriction but a little more height is available.

The most common applications for stacked-die packages are in portable electronic devices such as cellphones, PDAs, camcorders and other wireless consumer systems.

Figure 2a

Figure 2b

Figure 2c

Figure 2d

Figure 2e

The System-in-Package (SiP) approach is becoming increasingly popular not only for its very high density but because as passive component sizes shrink the devices become increasingly difficult and expensive to handle. Ceramic capacitors that measure 1mm x 0.5mm are now in common use and devices down to 0.4mm x 0.2mm are available in values up to 1000pF at 6.3Vdc. However, the cost of capital equipment to handle such tiny parts can make it difficult to find an economic way to take advantage of the available miniaturization. The SiP approach combines multiple ICs, discrete semiconductors and passive components onto a single package, providing a complete functional system in one module that can be processed much like a standard component during board assembly. It's not like SoC, which employs a single die. SiP packages are integrated by stacking or placing chips and components on a substrate, typically a BGA laminate or QFP lead-frame (Figure 2e). SiP has performance and size advantages over component level designs. In digital circuits, it can provide better memory bandwidth than SoC-based designs too, while in analog and mixed-signal designs the close proximity of passive and active parts minimizes stray capacitance and unwanted inductance to optimize high-speed signal performance.

SiP products are sometimes developed in custom packages but many can be accommodated in standard package outlines including BGA, QFP and QFN.

Some MPW service providers now deliver much more than bare die. Several, including MOSIS, are able to provide greater added value in helping you to achieve a successful chip, or SiP outcome. And because experienced MPW providers have completed many thousands of designs, their experience can be used to not only reduce your costs but also to give your next device competitive advantage through a packaging choice that optimizes both its performance and customer appeal. Silicon's only the start.

- Wes Hansford
Deputy Director
MOSIS Integrated Circuit Fabrication Service

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