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Synopsys heralds 2-3x speed boost with IC Compiler release

Posted: 06 Oct 2008 ?? ?Print Version ?Bookmark and Share

Keywords:compiler IC? speed-up 3x? DFM?

Claiming a 2x to 3x speed-up in overall design turnaround time compared to the previous release, Synopsys Inc. introduced last week the IC Compiler 2008.09.

Synopsys said the new release introduces new technology that speeds design closure, including improved timing, variation-aware clock-tree synthesis, lower power, enhanced DFM, and signoff-quality incremental design- rule checking.

Beginning with this release, Synopsys' Zroute multithreaded router technology, announced earlier this year, is now available as a standard feature to all IC Compiler customers, Synopsys said.

Compared to the prior release (2007.03), the new IC Compiler 2008.09 release has demonstrated an average speed-up of 2x across a broad set of customer designs, Synopsys said. A total of 3x speed-up may be achieved by enabling multithreading on quad-core machines that are commonly used in the IC Compiler customer base, the company said.

Synopsys said it has observed even higher speed-up in select customer cases through methodology review and optimization.

"Speeding up turnaround time has been a key target for us, and IC Compiler 2008.09 delivers a major installment towards this target," said Antun Domic, senior VP and general manager of the Synopsys Implementation group, in a statement.

- Dylan McGrath
EE Times

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