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Assembly and PCB layout guidelines for chip-scale packages

Posted: 06 Oct 2008 ?? ?Print Version ?Bookmark and Share

Keywords:PCB? chips-scale package? CSP?

The chip-scale package (CSP) is a dual- or multilayer plastic encapsulated BT-Epoxy type substrate with copper signal and plain layers. The small form factor allows for enhanced conduction of heat to the PCB and provides a stable ground through down bonds; as well as an electrical connection through conductive, die-attached material. The design of these dual- and multilayer small body packages allows for flexibility and enhances electrical performance to high-speed operating frequency.

Actel offers CSPs in multiple configurations: substrate ball pitch range from 0.4mm to 0.8mm, with a package body size of 4mm x 4mm to 14mm x 14mm, and overall package height of 0.73mm to 1.35mm. The package footprint and outlines are specified in JEDEC MO-195, JEDEC MO-205, and JEDEC Design Guide 4.5 "Fine-Pitch, Square Ball Grid Array Package (FBGA)".

This application note provides general guidelines for proper board design and surface-mount process.

View the PDF document for more information.

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