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Panasonic, Renesas bring partnership to 32nm

Posted: 13 Oct 2008 ?? ?Print Version ?Bookmark and Share

Keywords:32nm partnership? next-gen process? technology transistor?

Building on their partnership on the joint process technology development since 1998, Panasonic Corp. and Renesas Technology Corp. are now collaborating on the development of elemental process technologies for SoCs of the next-generation 32nm node. The two companies hope that their 32nm node transistor technology and other advances can soon be applied to products in mass production.

The two partners have been working on the joint development of next-generation SoC technology, even before the establishment of Renesas Technology. They developed a 130nm DRAM composite process in 2001, a 90nm SoC process in 2002, a 90nm DRAM composite process in 2004, a 65nm SoC process in 2005, and a 45nm SoC process in 2007.

The latest development on the new 32nm fabrication process will be applied to SoCs for advanced mobile and digital home appliance products.

32nm promises
The new 32nm SoC process employs a newly developed transistor technology with a metal/high-k1 gate stack structure and interconnect technology, using a new ultralow-k2 material. To achieve a device using complementary metal-insulator semiconductor (CMIS) technology, a type of CMOS, at a 32nm node, an ultrathin film cap layer is applied at the atomic level to transistors with a metal/high-k gate stack structure under optimized conditions. This allows development of a conventional transistor configuration, employing an oxidized silicon film as the gate insulation layer. The introduction of the cap layer has been shown to improve transistor reliability in practical use and suppress distribution of electrical characteristics between transistors, thereby enabling the operation of large-scale circuits.





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