Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > FPGAs/PLDs
?
?
FPGAs/PLDs??

Physical interface to QDRII memories using Actel ProASIC 3E FPGAS

Posted: 22 Oct 2008 ?? ?Print Version ?Bookmark and Share

Keywords:interface physical? QDRII memory? FPGA?

Quad Data Rate (QDR) memories are a family of memory products defined and developed by the QDR Consortium comprised of Cypress, Hitachi, IDT, Micron, NEC, and Samsung. QDR memories have been developed mainly to address increasing demand for high data bandwidth in today's high speed applications. QDR memories achieve high data transfer rates by providing two independent data paths.

One path for read data and another for write data. Each data path uses Double Data Rate (DDR) operation to transfer data. Thus QDR memories effectively transfer four data words (two words on read paths and two words on write paths) in a single clock cycle. This application note shows how to implement a physical interface to QDRII memories in Actel's ProASIC3E devices, as well as IGLOOe devices, and A3PE3000L device (ProASIC3L family).

View the PDF document for more information.





Article Comments - Physical interface to QDRII memories...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top