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Simulation tool upgrades multicore architectures

Posted: 24 Oct 2008 ?? ?Print Version ?Bookmark and Share

Keywords:analog? EDA?

Gemini Design Automation, an EDA start-up that has spent the last three years under wraps, has released its simulation technology. With an objective of finding solutions to the challenge of verifying complex analog and mixed-signal designs, Gemini developed a simulator that improves both speed and accuracy. It is a claim that one might be tempted to take with a pinch of salt, if not for the past experience of the company's founders and support by Jim Solomon, one of the popular names in the EDA world and Cadence cofounder.

Along with Gemini's capacities are multithreading and parallel computation techniques, developed by Baolin Yang, founder, Gemini, that make use of today's multicore computing architectures. Compared to other multithreaded simulators in the market, Gemini threads both the model evaluation and matrix solving components of the simulator.

Kent Jaeger, VP of marketing and sales, Gemini, said Synopsis' H Spice threads the matrix and give solutions to some degree, while Cadence's Spectre Turbo Plus, the simulator against which Gemini's solution is typically benchmarked by potential customers, is part threaded. "They have only threaded model evaluation," Jaeger said. "We run two to 10 times faster than any of those first generation approaches, significantly faster than Cadence Spectre Turbo Plus, while there is no comparison with non-threaded simulators," he added.

Gemini's market advantage
It was expected that Gemini's solution would be compared to Spectre. As the one responsible for starting Cadence's analog division and partly or even wholly the brain for the creation of Spectre, Solomon said, "Our starting goal was to build something that gave exactly the same answer as Spectre, i.e. to replicate the same accuracy, but do it faster. However, this was started from the ground up and Gemini was not hamstrung by history." In practice, this means that although Yang, himself, an ex-Cadence, having worked within the Spectre development group and the rest of the development team have tedious knowledge of past SPICE simulators, they are using new, although undisclosed techniques to achieve the capacity gains that Gemini is claiming.

"Although there was a temptation to use FastMOS techniques, we put a hard rule on the developers that they could not use any because it would compromise the robustness of simulator. We wanted to develop something that works correctly every time," Solomon recounted.

The goal to succeed
Gemini considers that its tool effectively straddles the FastMOS and SPICE accurate tool arena. "We believe we can be in a lead position in the SPICE accurate arena because our tool targets 95 percent of SPICE accurate seats," the company said. "But we think we can also target a large part of the FastMOS sector because we run so fast," said Jaeger.

As a fully threaded application, the tool's performance is believed to scale linearly with additional cores, while its matrix computation time scales with the size and complexity of circuit matrices, making it more effective for large designs with high parasitic count. One customer group that Gemini has focused on is in the 10Gbyte Ethernet SoC arena.

"These designs might consist of about 40 million transistors, where only one million are analogs. However, the die area used by the analog portion of the chip is around 15 percent of the total. When you started talking about the verification issue with these customers, we found that the percentage of verification time accounted for by the analog and mixed-signal portions of the chip has become their biggest challenge. The breadth and complexity of analog functions is increasing," Jaeger said.

Gemini said its tool, which will be released during Q4 08, is ideal for simulating functions such as PLLs, ADCs and DAC's, charge pumps, programmable Tx/Rx chains, power distribution circuitry, and memory IP - designs that have a large number of extracted post-layout parasitics. It runs on standard X86 SMP multicore platforms equipped with 64bit Linux OS. Although the company recommends the customers to use a quad core platform, it can run on two or a single core.

- Vanessa Knivett
EE Times





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