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Ziptronix heralds 3-D chip stacking technique

Posted: 31 Oct 2008 ?? ?Print Version ?Bookmark and Share

Keywords:3-D? DBI?

Ziptronix unveiled details of its patented Direct Bond Interconnect (DBI) technology, which employs a low-temperature process for 3-D chip stacking without thermal compression.

Ziptronix said the technology can be used for either wafer-to-wafer or chip-to-wafer stacking, further claiming that its 3-D bonding process is low-cost and provides high yields.

The details were revealed in U.S. Patent 7,387,944 (on low temperature covalent bonding) and U.S. Patent 6,962,835 (on the direct bond interconnect). Based on through-silicon vias (TSVs), the company claims its low-temperature oxide bond provides a metal-to-metal contact for vias, without the high temperatures necessary when using thermal compression techniques.

According Yole Development, the typical fab running 500,000 300mm wafers per year using 1 micron-by-20 micron vias could bond wafers using the Ziptronix DBI technology for $12 per wafer, compared to $22 for adhesive techniques and $57 for high-temperature copper-to-copper thermal compression. The Ziptronix technique works with copper, tungsten or aluminum TSVs on either backside or frontside interconnects.

The Ziptronix DBI technology is available for license to original equipment manufacturers and integrated device manufacturers for any CMOS chip.

- R. Colin Johnson
EE Times

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