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Chips reembrace multicore architecture

Posted: 03 Nov 2008 ?? ?Print Version ?Bookmark and Share

Keywords:multicore architecture? DSP? processor?

Adding cores to a processor to gain a performance boost, while lowering power demand, has become standard practice in the computing and embedded processor industries. While a similar evolution seems inevitable for all types of high-performance processing, prior experience has made DSP vendors more selective in applying the multicore approach. DSPs are now beginning to reembrace multicore architectures, but mainly for specific applications possessing well-partitioned processing tasks.

Perform partitioning
A DSP application often comprises only a few highly complex tasks, and system performance improvements depend on hastening task execution, not simply running more tasks. Instead of partitioning at the task level, this system often requires partitioning at the algorithm level. The overall task, such as compressing a video stream, must be broken into steps that can run in parallel on separate cores. The task scheduler or OS cannot perform such partitioning; it must come during the software design. Many DSP application developers avoid the multicore approach because of the difficulty of algorithm partitioning. At the same time, some tasks such as encryption are not suitable to parallelization.

Many developers avoid the multicore approach because of the difficulty of algorithm partitioning.

Homogenous vs. heterogeneous
This doesn't mean that the multicore approach hasn't been tried with DSPs. PicoChip has long had its picoArray architecture that puts multiple, identical cores together for high-performance DSP. In most cases, however, multicore design offerings with DSP had not been homogeneoushaving multiple copies of the same core. Instead, they integrated a DSP core with a RISC CPU core. Such heterogeneous DSPs, for instance, have been part of multicore processor designs for a number of years in the handsets and communications industries. The applications these processors targeted readily separate into signal processing tasks for the DSP and control tasks for the RISC CPU, making partitioning more direct.

One exception was the Blackfin BF561 dual-core DSP from Analog Devices Inc. The device used cores that were designed to handle both types of tasks well, so there was no need to partition along task lines. Instead, developers could assign tasks according to their preference to balance the load among the cores. Most developers at the time, however, were inexperienced at partitioning software and automated tool support was lacking, so the homogeneous multicore DSP was not quickly adopted.

"The BF561 was an early entrant to the field," said David Katz, ADI's Blackfin applications manager, "and it was ahead of its time. It has taken a while for people to learn partitioning." He noted that it has not introduced a homogeneous multicore DSP design since the BF561, although "multicore is an important part of our roadmap strategy."

Other DSP vendors also view multicore as an inevitable trend for DSPs, for the same reason it was adopted in computing: higher performance at lower power. What is now making homogeneous multicore DSP chip designs appear once more is a shift in the performance increases some systems require. In some applications, the need for performance is moving from performing a single task faster to performing more tasks. This shift is simplifying DSP task partitioning, making it more like that of other embedded applications, and DSP vendors are creating products that capitalize on the opportunity.

Processing change
With the rising demand for VoIP and video over IP, media processing has become one such shifting application. A media gateway design, for instance, must provide a number of voice, audio and video codecs, and handle multiple independent channels. This application structure is easily partitioned into independent tasks, making it a good fit for multicore DSP designs.

The Octasic Vocallo addresses this application space. Vocallo has 15 identical DSP cores, giving designers considerable flexibility in creating parallel and pipelined architectures that strike the right balance of channel capacity for different installations.

Another multicore DSP for communications is Texas Instruments Inc.'s TNETV3020 for high-density core networks. "What we are doing now is application-specific multiprocessing," said Ray Simar, manager of multicore solutions at TI. "In infrastructure applications you're doing the same tasks, so designs can gravitate to multiple copies of the same processor."

The TNETV3020 has six DSP cores, along with a switch fabric and a variety of serial I/O channels, allowing designers to configure the design for tasks such as channel format conversion.

Communications is not the only DSP application changing its character. Audio processing has also grown to require high-performance handling of multiple tasks that are needed for simple partitioning among multiple cores. According to Sujata Neidig, audio DSP product manager at Freescale Semiconductor Inc., the advent of high-definition, Dolby and Blu-ray audio algorithms has increased performance demands on audio DSPs as much as five times, with rising complexity, data rates and numbers of channels. Further, Neidig said more features such as automatic volume control are being integrated to audio.

Recycling codes
Freescale's Symphony DSP56724 and DSP56725 DSPs offer a dual-core architecture that allows developers to split the processing burden while reusing their existing code. Multicore DSPs that target video or mixed audio and video processing are also appearing. Samples are the CT3616 from Cradle Technologies Inc., the Voyageur from Gennum Corp. and multicore DSPs for audio from Cirrus Logic Inc.

The trend toward multicore DSP chip designs may ultimately move the partitioning task out of the developers' hands into the chip vendors'. An example is the PC302, recently introduced by PicoChip. The company used its general-purpose picoArray architecture to create a device that implements a complete femtocell access point on a single chip. The company handled all the partitioning and put the core system software in on-chip memory, limiting developers' efforts to add custom functionality.

Such specialized devices may be the near-term future for multicore DSP designs, but long term the multicore approach will envelope general-purpose DSP designs as well. "As we look down the road we can see that multicore for DSP is not a one-trick pony," said Simar. "It will become more common."

Along with that shift will come a growing need for developers to learn how to partition their designs to effectively utilize homogenous multicore DSPs. "A number of people want a compiler to handle this," said Simar, "but that's not going to happen for a while. We will need to think about things differently in order to apply these devices."

Richard Quinnell
EE Times

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