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Carry out cache coherence in a MIPS32 multicore design

Posted: 03 Nov 2008 ?? ?Print Version ?Bookmark and Share

Keywords:MIPS32? multicore design? embedded?

Historically, memory coherence in multiprocessor systems was often achieved through bus "snooping." In snooping, each core was connected to a common multi-tier bus and was able to snoop on memory-access traffic of processor peers to regulate the coherence status of individual cache lines. Each core maintained the coherence status of L1 cache lines locally and posted status changes to peers via the common bus.

The increasing size and complexity of the SoC led to restructuring of the multi-tier-bus philosophy in favor of localized point-to-point connections with centralized traffic routing. This configuration enabled speed and power improvements on now localized bus segments due to reduced load and segment length. Also, bus-contention problems eased, and throughput increased for the localized data exchange. In response to this trend in system architecture, the Open Core Protocol (OCP) standard emerged to consolidate this design philosophy. Furthermore, emergence of IP-provider business models catalyzed the standardization of IP interconnect and design methods to facilitate design reuse centered on an open standard.

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